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[/] [or1k/] [tags/] [rel_21/] [or1200/] [rtl/] [verilog/] - Rev 595

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Rev Log message Author Age Path
595 Fixed 'the NPC single-step fix'. lampret 8246d 11h /or1k/tags/rel_21/or1200/rtl/verilog/
589 No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC. lampret 8246d 18h /or1k/tags/rel_21/or1200/rtl/verilog/
573 Fixed module name when compiling with OR1200_XILINX_RAM32X1D lampret 8249d 19h /or1k/tags/rel_21/or1200/rtl/verilog/
571 Changed alignment exception EPCR. Not tested yet. lampret 8250d 04h /or1k/tags/rel_21/or1200/rtl/verilog/
570 Fixed order of syscall and range exceptions. lampret 8250d 06h /or1k/tags/rel_21/or1200/rtl/verilog/
569 Default ASIC configuration does not sample WB inputs. lampret 8250d 16h /or1k/tags/rel_21/or1200/rtl/verilog/
562 Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if. lampret 8250d 19h /or1k/tags/rel_21/or1200/rtl/verilog/
536 Fixed typo. OR1200_REGISTERED_OUTPUTS was not defined. Should be. lampret 8257d 01h /or1k/tags/rel_21/or1200/rtl/verilog/
512 Uncommented OR1200_REGISTERED_OUTPUTS for FPGA target. lampret 8261d 04h /or1k/tags/rel_21/or1200/rtl/verilog/
504 New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs. lampret 8261d 17h /or1k/tags/rel_21/or1200/rtl/verilog/
402 Added OR1200_GENERIC_MULTP2_32X32 and OR1200_ASIC_MULTP2_32X32 lampret 8291d 20h /or1k/tags/rel_21/or1200/rtl/verilog/
401 *** empty log message *** simons 8295d 07h /or1k/tags/rel_21/or1200/rtl/verilog/
400 force_dslot_fetch does not work - allways zero. simons 8295d 07h /or1k/tags/rel_21/or1200/rtl/verilog/
399 Trap insn couses break after exits ex_insn. simons 8295d 07h /or1k/tags/rel_21/or1200/rtl/verilog/
391 Fixed except_stop width and fixed EX PC for 1400444f no-ops. lampret 8298d 02h /or1k/tags/rel_21/or1200/rtl/verilog/
390 Changed instantiation name of VS RAMs. lampret 8298d 04h /or1k/tags/rel_21/or1200/rtl/verilog/
387 Now FPGA and ASIC target are separate. lampret 8298d 06h /or1k/tags/rel_21/or1200/rtl/verilog/
386 Fixed VS RAM instantiation - again. lampret 8298d 06h /or1k/tags/rel_21/or1200/rtl/verilog/
370 Program counter divided to PPC and NPC. simons 8302d 04h /or1k/tags/rel_21/or1200/rtl/verilog/
367 Changed DSR/DRR behavior and exception detection. lampret 8302d 17h /or1k/tags/rel_21/or1200/rtl/verilog/
365 Added wb_cyc_o assignment after it was removed by accident. lampret 8303d 12h /or1k/tags/rel_21/or1200/rtl/verilog/
360 Added OR1200_REGISTERED_INPUTS. lampret 8305d 04h /or1k/tags/rel_21/or1200/rtl/verilog/
359 Added optional sampling of inputs. lampret 8305d 04h /or1k/tags/rel_21/or1200/rtl/verilog/
358 Fixed virtual silicon single-port rams instantiation. lampret 8305d 04h /or1k/tags/rel_21/or1200/rtl/verilog/
357 Fixed dbg_is_o assignment width. lampret 8305d 04h /or1k/tags/rel_21/or1200/rtl/verilog/
356 Break point bug fixed simons 8305d 07h /or1k/tags/rel_21/or1200/rtl/verilog/
354 Fixed width of du_except. lampret 8306d 01h /or1k/tags/rel_21/or1200/rtl/verilog/
353 Cashes disabled. simons 8306d 11h /or1k/tags/rel_21/or1200/rtl/verilog/
352 OR1200_REGISTERED_OUTPUTS can now be enabled. lampret 8307d 14h /or1k/tags/rel_21/or1200/rtl/verilog/
351 Fixed some l.trap typos. lampret 8307d 16h /or1k/tags/rel_21/or1200/rtl/verilog/

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