OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_24/] [or1200/] - Rev 1175

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
1175 Added three missing wire declarations. No functional changes. lampret 7657d 13h /or1k/tags/rel_24/or1200/
1172 Added embedded memory QMEM. lampret 7659d 23h /or1k/tags/rel_24/or1200/
1171 Added embedded memory QMEM. lampret 7659d 23h /or1k/tags/rel_24/or1200/
1163 This commit was manufactured by cvs2svn to create branch 'branch_qmem'. 7692d 11h /or1k/tags/rel_24/or1200/
1161 When OR1200_NO_IMMU and OR1200_NO_IC are not both defined or undefined at the same time, results in a IC bug. Fixed. lampret 7692d 11h /or1k/tags/rel_24/or1200/
1159 No functional changes. Added defines to disable implementation of multiplier/MAC lampret 7735d 14h /or1k/tags/rel_24/or1200/
1155 No functional change. Only added customization for exception vectors. lampret 7738d 16h /or1k/tags/rel_24/or1200/
1140 Fixed OR1200_CLKDIV_x_SUPPORTED defines. Fixed order of ifdefs. lampret 7751d 17h /or1k/tags/rel_24/or1200/
1139 Fixed OR1200_CLKDIV_x_SUPPORTED defines. Better description. lampret 7751d 17h /or1k/tags/rel_24/or1200/
1132 RFRAM defines comments updated. Altera LPM option added. lampret 7752d 13h /or1k/tags/rel_24/or1200/
1131 Added another pipe stage to match gmult. One day second pipe in amult and gmult might be removed to get better performance. lampret 7752d 13h /or1k/tags/rel_24/or1200/
1130 RFRAM type always need to be defined. lampret 7752d 13h /or1k/tags/rel_24/or1200/
1129 Added Altera LPM RAMs. Changed generic RAM output when OE inactive. lampret 7752d 13h /or1k/tags/rel_24/or1200/
1112 Updated sensitivity list for trace buffer [only relevant for Xilinx FPGAs] lampret 7827d 11h /or1k/tags/rel_24/or1200/
1104 Added optional support for WB B3 specification (xwb_cti_o, xwb_bte_o). Made xwb_cab_o optional. lampret 7872d 05h /or1k/tags/rel_24/or1200/
1083 SB mem width fixed. simons 7904d 01h /or1k/tags/rel_24/or1200/
1079 RAMs wrong connected to the BIST scan chain. mohor 7912d 22h /or1k/tags/rel_24/or1200/
1078 Previous check-in was done by mistake. mohor 7912d 23h /or1k/tags/rel_24/or1200/
1077 Signal scanb_sen renamed to scanb_en. mohor 7912d 23h /or1k/tags/rel_24/or1200/
1069 Signal scanb_eni renamed to scanb_en mohor 7916d 16h /or1k/tags/rel_24/or1200/
1063 Added BIST scan. Special VS RAMs need to be used to implement BIST. lampret 7923d 18h /or1k/tags/rel_24/or1200/
1055 Removed obsolete comment. lampret 7955d 11h /or1k/tags/rel_24/or1200/
1054 Fixed a combinational loop. lampret 7955d 11h /or1k/tags/rel_24/or1200/
1053 Disabled cache inhibit atttribute. lampret 7955d 11h /or1k/tags/rel_24/or1200/
1040 Updated the script. lampret 7962d 17h /or1k/tags/rel_24/or1200/
1039 Added linter directory. lampret 7962d 17h /or1k/tags/rel_24/or1200/
1038 Fixed a typo, reported by Taylor Su. lampret 7962d 19h /or1k/tags/rel_24/or1200/
1037 First import of the new synopsys DC scripts. lampret 7962d 20h /or1k/tags/rel_24/or1200/
1036 Removed old synthesis scripts. lampret 7962d 20h /or1k/tags/rel_24/or1200/
1035 Added optional l.div/l.divu insns. By default they are disabled. lampret 7963d 09h /or1k/tags/rel_24/or1200/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.