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[/] [or1k/] [tags/] [rel_25/] [or1200/] [rtl/] [verilog/] - Rev 1129

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Rev Log message Author Age Path
1129 Added Altera LPM RAMs. Changed generic RAM output when OE inactive. lampret 7795d 10h /or1k/tags/rel_25/or1200/rtl/verilog/
1112 Updated sensitivity list for trace buffer [only relevant for Xilinx FPGAs] lampret 7870d 08h /or1k/tags/rel_25/or1200/rtl/verilog/
1104 Added optional support for WB B3 specification (xwb_cti_o, xwb_bte_o). Made xwb_cab_o optional. lampret 7915d 03h /or1k/tags/rel_25/or1200/rtl/verilog/
1083 SB mem width fixed. simons 7946d 22h /or1k/tags/rel_25/or1200/rtl/verilog/
1079 RAMs wrong connected to the BIST scan chain. mohor 7955d 19h /or1k/tags/rel_25/or1200/rtl/verilog/
1078 Previous check-in was done by mistake. mohor 7955d 20h /or1k/tags/rel_25/or1200/rtl/verilog/
1077 Signal scanb_sen renamed to scanb_en. mohor 7955d 21h /or1k/tags/rel_25/or1200/rtl/verilog/
1069 Signal scanb_eni renamed to scanb_en mohor 7959d 13h /or1k/tags/rel_25/or1200/rtl/verilog/
1063 Added BIST scan. Special VS RAMs need to be used to implement BIST. lampret 7966d 16h /or1k/tags/rel_25/or1200/rtl/verilog/
1055 Removed obsolete comment. lampret 7998d 08h /or1k/tags/rel_25/or1200/rtl/verilog/
1054 Fixed a combinational loop. lampret 7998d 08h /or1k/tags/rel_25/or1200/rtl/verilog/
1053 Disabled cache inhibit atttribute. lampret 7998d 08h /or1k/tags/rel_25/or1200/rtl/verilog/
1038 Fixed a typo, reported by Taylor Su. lampret 8005d 16h /or1k/tags/rel_25/or1200/rtl/verilog/
1035 Added optional l.div/l.divu insns. By default they are disabled. lampret 8006d 06h /or1k/tags/rel_25/or1200/rtl/verilog/
1033 If SR[CY] implemented with OR1200_IMPL_ADDC enabled, l.add/l.addi also set SR[CY]. lampret 8006d 16h /or1k/tags/rel_25/or1200/rtl/verilog/
1032 Added optional SR[CY]. Added define to enable additional (compare) flag modifiers. Defines are OR1200_IMPL_ADDC and OR1200_ADDITIONAL_FLAG_MODIFIERS. lampret 8007d 06h /or1k/tags/rel_25/or1200/rtl/verilog/
1023 Now most of the configuration registers are updatded automatically based on defines in or1200_defines.v. lampret 8010d 11h /or1k/tags/rel_25/or1200/rtl/verilog/
1022 As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy. lampret 8010d 13h /or1k/tags/rel_25/or1200/rtl/verilog/
1011 Removed some commented RTL. Fixed SR/ESR flag bug. lampret 8017d 10h /or1k/tags/rel_25/or1200/rtl/verilog/
994 Store buffer has been tested and it works. BY default it is still disabled until uClinux confirms correct operation on FPGA board. lampret 8023d 09h /or1k/tags/rel_25/or1200/rtl/verilog/
993 Fixed IMMU bug. lampret 8023d 09h /or1k/tags/rel_25/or1200/rtl/verilog/
984 Disable SB until it is tested lampret 8026d 14h /or1k/tags/rel_25/or1200/rtl/verilog/
977 Added store buffer. lampret 8026d 16h /or1k/tags/rel_25/or1200/rtl/verilog/
962 Fixed Xilinx trace buffer address. REported by Taylor Su. lampret 8030d 06h /or1k/tags/rel_25/or1200/rtl/verilog/
958 Disabled ITLB translation when 1) doing access to ITLB SPRs or 2) crossing page. This modification was tested only with parts of IMMU test - remaining test cases needs to be run. lampret 8031d 05h /or1k/tags/rel_25/or1200/rtl/verilog/
944 Added OR1200_WB_RETRY. Moved WB registered outsputs / samples inputs into lower section. lampret 8033d 06h /or1k/tags/rel_25/or1200/rtl/verilog/
943 Added optional retry counter for wb_rty_i. Added graceful termination for aborted transfers. lampret 8033d 06h /or1k/tags/rel_25/or1200/rtl/verilog/
942 Delayed external access at page crossing. lampret 8033d 06h /or1k/tags/rel_25/or1200/rtl/verilog/
916 MAC now follows software convention (signed multiply instead of unsigned). lampret 8045d 10h /or1k/tags/rel_25/or1200/rtl/verilog/
895 Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized. lampret 8061d 13h /or1k/tags/rel_25/or1200/rtl/verilog/

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