OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_26/] [or1200/] [rtl/] - Rev 1155

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
1155 No functional change. Only added customization for exception vectors. lampret 7788d 05h /or1k/tags/rel_26/or1200/rtl/
1140 Fixed OR1200_CLKDIV_x_SUPPORTED defines. Fixed order of ifdefs. lampret 7801d 06h /or1k/tags/rel_26/or1200/rtl/
1139 Fixed OR1200_CLKDIV_x_SUPPORTED defines. Better description. lampret 7801d 06h /or1k/tags/rel_26/or1200/rtl/
1132 RFRAM defines comments updated. Altera LPM option added. lampret 7802d 02h /or1k/tags/rel_26/or1200/rtl/
1131 Added another pipe stage to match gmult. One day second pipe in amult and gmult might be removed to get better performance. lampret 7802d 02h /or1k/tags/rel_26/or1200/rtl/
1130 RFRAM type always need to be defined. lampret 7802d 02h /or1k/tags/rel_26/or1200/rtl/
1129 Added Altera LPM RAMs. Changed generic RAM output when OE inactive. lampret 7802d 02h /or1k/tags/rel_26/or1200/rtl/
1112 Updated sensitivity list for trace buffer [only relevant for Xilinx FPGAs] lampret 7877d 00h /or1k/tags/rel_26/or1200/rtl/
1104 Added optional support for WB B3 specification (xwb_cti_o, xwb_bte_o). Made xwb_cab_o optional. lampret 7921d 18h /or1k/tags/rel_26/or1200/rtl/
1083 SB mem width fixed. simons 7953d 13h /or1k/tags/rel_26/or1200/rtl/
1079 RAMs wrong connected to the BIST scan chain. mohor 7962d 11h /or1k/tags/rel_26/or1200/rtl/
1078 Previous check-in was done by mistake. mohor 7962d 12h /or1k/tags/rel_26/or1200/rtl/
1077 Signal scanb_sen renamed to scanb_en. mohor 7962d 12h /or1k/tags/rel_26/or1200/rtl/
1069 Signal scanb_eni renamed to scanb_en mohor 7966d 05h /or1k/tags/rel_26/or1200/rtl/
1063 Added BIST scan. Special VS RAMs need to be used to implement BIST. lampret 7973d 07h /or1k/tags/rel_26/or1200/rtl/
1055 Removed obsolete comment. lampret 8005d 00h /or1k/tags/rel_26/or1200/rtl/
1054 Fixed a combinational loop. lampret 8005d 00h /or1k/tags/rel_26/or1200/rtl/
1053 Disabled cache inhibit atttribute. lampret 8005d 00h /or1k/tags/rel_26/or1200/rtl/
1038 Fixed a typo, reported by Taylor Su. lampret 8012d 08h /or1k/tags/rel_26/or1200/rtl/
1035 Added optional l.div/l.divu insns. By default they are disabled. lampret 8012d 21h /or1k/tags/rel_26/or1200/rtl/
1033 If SR[CY] implemented with OR1200_IMPL_ADDC enabled, l.add/l.addi also set SR[CY]. lampret 8013d 08h /or1k/tags/rel_26/or1200/rtl/
1032 Added optional SR[CY]. Added define to enable additional (compare) flag modifiers. Defines are OR1200_IMPL_ADDC and OR1200_ADDITIONAL_FLAG_MODIFIERS. lampret 8013d 22h /or1k/tags/rel_26/or1200/rtl/
1023 Now most of the configuration registers are updatded automatically based on defines in or1200_defines.v. lampret 8017d 02h /or1k/tags/rel_26/or1200/rtl/
1022 As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy. lampret 8017d 05h /or1k/tags/rel_26/or1200/rtl/
1011 Removed some commented RTL. Fixed SR/ESR flag bug. lampret 8024d 02h /or1k/tags/rel_26/or1200/rtl/
994 Store buffer has been tested and it works. BY default it is still disabled until uClinux confirms correct operation on FPGA board. lampret 8030d 01h /or1k/tags/rel_26/or1200/rtl/
993 Fixed IMMU bug. lampret 8030d 01h /or1k/tags/rel_26/or1200/rtl/
984 Disable SB until it is tested lampret 8033d 05h /or1k/tags/rel_26/or1200/rtl/
977 Added store buffer. lampret 8033d 07h /or1k/tags/rel_26/or1200/rtl/
962 Fixed Xilinx trace buffer address. REported by Taylor Su. lampret 8036d 21h /or1k/tags/rel_26/or1200/rtl/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.