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[/] [or1k/] [tags/] [rel_26/] [or1200/] [rtl/] [verilog/] - Rev 1032

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Rev Log message Author Age Path
1032 Added optional SR[CY]. Added define to enable additional (compare) flag modifiers. Defines are OR1200_IMPL_ADDC and OR1200_ADDITIONAL_FLAG_MODIFIERS. lampret 7983d 16h /or1k/tags/rel_26/or1200/rtl/verilog/
1023 Now most of the configuration registers are updatded automatically based on defines in or1200_defines.v. lampret 7986d 21h /or1k/tags/rel_26/or1200/rtl/verilog/
1022 As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy. lampret 7986d 23h /or1k/tags/rel_26/or1200/rtl/verilog/
1011 Removed some commented RTL. Fixed SR/ESR flag bug. lampret 7993d 20h /or1k/tags/rel_26/or1200/rtl/verilog/
994 Store buffer has been tested and it works. BY default it is still disabled until uClinux confirms correct operation on FPGA board. lampret 7999d 19h /or1k/tags/rel_26/or1200/rtl/verilog/
993 Fixed IMMU bug. lampret 7999d 19h /or1k/tags/rel_26/or1200/rtl/verilog/
984 Disable SB until it is tested lampret 8002d 23h /or1k/tags/rel_26/or1200/rtl/verilog/
977 Added store buffer. lampret 8003d 01h /or1k/tags/rel_26/or1200/rtl/verilog/
962 Fixed Xilinx trace buffer address. REported by Taylor Su. lampret 8006d 15h /or1k/tags/rel_26/or1200/rtl/verilog/
958 Disabled ITLB translation when 1) doing access to ITLB SPRs or 2) crossing page. This modification was tested only with parts of IMMU test - remaining test cases needs to be run. lampret 8007d 15h /or1k/tags/rel_26/or1200/rtl/verilog/
944 Added OR1200_WB_RETRY. Moved WB registered outsputs / samples inputs into lower section. lampret 8009d 16h /or1k/tags/rel_26/or1200/rtl/verilog/
943 Added optional retry counter for wb_rty_i. Added graceful termination for aborted transfers. lampret 8009d 16h /or1k/tags/rel_26/or1200/rtl/verilog/
942 Delayed external access at page crossing. lampret 8009d 16h /or1k/tags/rel_26/or1200/rtl/verilog/
916 MAC now follows software convention (signed multiply instead of unsigned). lampret 8021d 19h /or1k/tags/rel_26/or1200/rtl/verilog/
895 Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized. lampret 8037d 23h /or1k/tags/rel_26/or1200/rtl/verilog/
871 Generic flip-flop based memory macro for register file. lampret 8074d 05h /or1k/tags/rel_26/or1200/rtl/verilog/
870 Added defines for enabling generic FF based memory macro for register file. lampret 8074d 05h /or1k/tags/rel_26/or1200/rtl/verilog/
869 Added generic flip-flop based memory macro instantiation. lampret 8074d 05h /or1k/tags/rel_26/or1200/rtl/verilog/
795 Added a directive to ignore signed division variables that are only used in simulation. lampret 8145d 05h /or1k/tags/rel_26/or1200/rtl/verilog/
794 Added again just recently removed full_case directive lampret 8145d 05h /or1k/tags/rel_26/or1200/rtl/verilog/
791 Fixed some ports in instnatiations that were removed from the modules lampret 8145d 05h /or1k/tags/rel_26/or1200/rtl/verilog/
790 Changed comment about synopsys to _synopsys_ because synthesis was complaining about unknown directives lampret 8145d 05h /or1k/tags/rel_26/or1200/rtl/verilog/
788 Some of the warnings fixed. lampret 8145d 06h /or1k/tags/rel_26/or1200/rtl/verilog/
778 Added second type of Virtual Silicon two-port SRAM (for register file). Changed defines for VS STP RAMs. lampret 8146d 02h /or1k/tags/rel_26/or1200/rtl/verilog/
777 Changed define name from OR1200_MEM2REG_FAST to OR1200_IMPL_MEM2REG2 lampret 8146d 02h /or1k/tags/rel_26/or1200/rtl/verilog/
776 Updated defines. lampret 8146d 02h /or1k/tags/rel_26/or1200/rtl/verilog/
775 Optimized cache controller FSM. lampret 8146d 02h /or1k/tags/rel_26/or1200/rtl/verilog/
774 Removed old files. lampret 8146d 03h /or1k/tags/rel_26/or1200/rtl/verilog/
737 Added alternative for critical path in DU. lampret 8160d 21h /or1k/tags/rel_26/or1200/rtl/verilog/
736 Changed generation of SPR address. Now it is ORed from base and offset instead of a sum. lampret 8163d 20h /or1k/tags/rel_26/or1200/rtl/verilog/

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