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[/] [or1k/] [tags/] [rel_27/] [or1200/] [rtl/] - Rev 870

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Rev Log message Author Age Path
870 Added defines for enabling generic FF based memory macro for register file. lampret 8091d 15h /or1k/tags/rel_27/or1200/rtl/
869 Added generic flip-flop based memory macro instantiation. lampret 8091d 15h /or1k/tags/rel_27/or1200/rtl/
795 Added a directive to ignore signed division variables that are only used in simulation. lampret 8162d 14h /or1k/tags/rel_27/or1200/rtl/
794 Added again just recently removed full_case directive lampret 8162d 15h /or1k/tags/rel_27/or1200/rtl/
791 Fixed some ports in instnatiations that were removed from the modules lampret 8162d 15h /or1k/tags/rel_27/or1200/rtl/
790 Changed comment about synopsys to _synopsys_ because synthesis was complaining about unknown directives lampret 8162d 15h /or1k/tags/rel_27/or1200/rtl/
788 Some of the warnings fixed. lampret 8162d 16h /or1k/tags/rel_27/or1200/rtl/
778 Added second type of Virtual Silicon two-port SRAM (for register file). Changed defines for VS STP RAMs. lampret 8163d 12h /or1k/tags/rel_27/or1200/rtl/
777 Changed define name from OR1200_MEM2REG_FAST to OR1200_IMPL_MEM2REG2 lampret 8163d 12h /or1k/tags/rel_27/or1200/rtl/
776 Updated defines. lampret 8163d 12h /or1k/tags/rel_27/or1200/rtl/
775 Optimized cache controller FSM. lampret 8163d 12h /or1k/tags/rel_27/or1200/rtl/
774 Removed old files. lampret 8163d 12h /or1k/tags/rel_27/or1200/rtl/
737 Added alternative for critical path in DU. lampret 8178d 07h /or1k/tags/rel_27/or1200/rtl/
736 Changed generation of SPR address. Now it is ORed from base and offset instead of a sum. lampret 8181d 06h /or1k/tags/rel_27/or1200/rtl/
735 Fixed async loop. Changed multiplier type for ASIC. lampret 8181d 06h /or1k/tags/rel_27/or1200/rtl/
668 Lapsus fixed. simons 8205d 16h /or1k/tags/rel_27/or1200/rtl/
663 No longer using async rst as sync reset for the counter. lampret 8208d 06h /or1k/tags/rel_27/or1200/rtl/
660 Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr. lampret 8209d 03h /or1k/tags/rel_27/or1200/rtl/
636 Fixed combinational loops. lampret 8218d 11h /or1k/tags/rel_27/or1200/rtl/
617 Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways. lampret 8223d 06h /or1k/tags/rel_27/or1200/rtl/
610 Changed default reset values for SR and ESR to match or1ksim's. Fixed flop model in or1200_dpram_32x32 when OR1200_XILINX_RAM32X1D is defined. lampret 8227d 23h /or1k/tags/rel_27/or1200/rtl/
597 Fixed OR1200_XILINX_RAM32X1D. lampret 8231d 17h /or1k/tags/rel_27/or1200/rtl/
596 SR[TEE] should be zero after reset. lampret 8231d 22h /or1k/tags/rel_27/or1200/rtl/
595 Fixed 'the NPC single-step fix'. lampret 8232d 17h /or1k/tags/rel_27/or1200/rtl/
589 No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC. lampret 8232d 23h /or1k/tags/rel_27/or1200/rtl/
573 Fixed module name when compiling with OR1200_XILINX_RAM32X1D lampret 8236d 01h /or1k/tags/rel_27/or1200/rtl/
571 Changed alignment exception EPCR. Not tested yet. lampret 8236d 10h /or1k/tags/rel_27/or1200/rtl/
570 Fixed order of syscall and range exceptions. lampret 8236d 12h /or1k/tags/rel_27/or1200/rtl/
569 Default ASIC configuration does not sample WB inputs. lampret 8236d 21h /or1k/tags/rel_27/or1200/rtl/
562 Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if. lampret 8237d 01h /or1k/tags/rel_27/or1200/rtl/

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