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[/] [or1k/] [tags/] [rel_29/] [or1200/] [rtl/] [verilog/] - Rev 504

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Rev Log message Author Age Path
504 New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs. lampret 8248d 04h /or1k/tags/rel_29/or1200/rtl/verilog/
402 Added OR1200_GENERIC_MULTP2_32X32 and OR1200_ASIC_MULTP2_32X32 lampret 8278d 07h /or1k/tags/rel_29/or1200/rtl/verilog/
401 *** empty log message *** simons 8281d 17h /or1k/tags/rel_29/or1200/rtl/verilog/
400 force_dslot_fetch does not work - allways zero. simons 8281d 17h /or1k/tags/rel_29/or1200/rtl/verilog/
399 Trap insn couses break after exits ex_insn. simons 8281d 17h /or1k/tags/rel_29/or1200/rtl/verilog/
391 Fixed except_stop width and fixed EX PC for 1400444f no-ops. lampret 8284d 13h /or1k/tags/rel_29/or1200/rtl/verilog/
390 Changed instantiation name of VS RAMs. lampret 8284d 15h /or1k/tags/rel_29/or1200/rtl/verilog/
387 Now FPGA and ASIC target are separate. lampret 8284d 16h /or1k/tags/rel_29/or1200/rtl/verilog/
386 Fixed VS RAM instantiation - again. lampret 8284d 16h /or1k/tags/rel_29/or1200/rtl/verilog/
370 Program counter divided to PPC and NPC. simons 8288d 14h /or1k/tags/rel_29/or1200/rtl/verilog/
367 Changed DSR/DRR behavior and exception detection. lampret 8289d 03h /or1k/tags/rel_29/or1200/rtl/verilog/
365 Added wb_cyc_o assignment after it was removed by accident. lampret 8289d 22h /or1k/tags/rel_29/or1200/rtl/verilog/
360 Added OR1200_REGISTERED_INPUTS. lampret 8291d 14h /or1k/tags/rel_29/or1200/rtl/verilog/
359 Added optional sampling of inputs. lampret 8291d 15h /or1k/tags/rel_29/or1200/rtl/verilog/
358 Fixed virtual silicon single-port rams instantiation. lampret 8291d 15h /or1k/tags/rel_29/or1200/rtl/verilog/
357 Fixed dbg_is_o assignment width. lampret 8291d 15h /or1k/tags/rel_29/or1200/rtl/verilog/
356 Break point bug fixed simons 8291d 17h /or1k/tags/rel_29/or1200/rtl/verilog/
354 Fixed width of du_except. lampret 8292d 11h /or1k/tags/rel_29/or1200/rtl/verilog/
353 Cashes disabled. simons 8292d 21h /or1k/tags/rel_29/or1200/rtl/verilog/
352 OR1200_REGISTERED_OUTPUTS can now be enabled. lampret 8294d 00h /or1k/tags/rel_29/or1200/rtl/verilog/
351 Fixed some l.trap typos. lampret 8294d 02h /or1k/tags/rel_29/or1200/rtl/verilog/
350 For GDB changed single stepping and disabled trap exception. lampret 8294d 03h /or1k/tags/rel_29/or1200/rtl/verilog/
338 Added 'setpc'. Renamed some signals (except_flushpipe into flushpipe etc) lampret 8299d 02h /or1k/tags/rel_29/or1200/rtl/verilog/
337 Fixed tick timer interrupt reporting by using TTCR[IP] bit. lampret 8299d 02h /or1k/tags/rel_29/or1200/rtl/verilog/
328 Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports. lampret 8300d 10h /or1k/tags/rel_29/or1200/rtl/verilog/
316 Fixed exceptions. lampret 8302d 08h /or1k/tags/rel_29/or1200/rtl/verilog/
271 Added missing endif lampret 8306d 21h /or1k/tags/rel_29/or1200/rtl/verilog/
265 Modified virtual silicon instantiations. lampret 8309d 17h /or1k/tags/rel_29/or1200/rtl/verilog/
220 Fixed parameters in generic sprams. lampret 8320d 16h /or1k/tags/rel_29/or1200/rtl/verilog/
219 Fixed sensitivity list. lampret 8321d 18h /or1k/tags/rel_29/or1200/rtl/verilog/

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