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[/] [or1k/] [tags/] [rel_3/] [or1200/] - Rev 1783

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Rev Log message Author Age Path
1765 root 5562d 12h /or1k/tags/rel_3/or1200/
995 This commit was manufactured by cvs2svn to create tag 'rel_3'. 7955d 09h /or1k/tags/rel_3/or1200/
994 Store buffer has been tested and it works. BY default it is still disabled until uClinux confirms correct operation on FPGA board. lampret 7955d 09h /or1k/tags/rel_3/or1200/
993 Fixed IMMU bug. lampret 7955d 09h /or1k/tags/rel_3/or1200/
984 Disable SB until it is tested lampret 7958d 13h /or1k/tags/rel_3/or1200/
977 Added store buffer. lampret 7958d 15h /or1k/tags/rel_3/or1200/
962 Fixed Xilinx trace buffer address. REported by Taylor Su. lampret 7962d 05h /or1k/tags/rel_3/or1200/
960 Directory cleanup. lampret 7962d 05h /or1k/tags/rel_3/or1200/
958 Disabled ITLB translation when 1) doing access to ITLB SPRs or 2) crossing page. This modification was tested only with parts of IMMU test - remaining test cases needs to be run. lampret 7963d 05h /or1k/tags/rel_3/or1200/
944 Added OR1200_WB_RETRY. Moved WB registered outsputs / samples inputs into lower section. lampret 7965d 05h /or1k/tags/rel_3/or1200/
943 Added optional retry counter for wb_rty_i. Added graceful termination for aborted transfers. lampret 7965d 05h /or1k/tags/rel_3/or1200/
942 Delayed external access at page crossing. lampret 7965d 05h /or1k/tags/rel_3/or1200/
916 MAC now follows software convention (signed multiply instead of unsigned). lampret 7977d 09h /or1k/tags/rel_3/or1200/
895 Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized. lampret 7993d 13h /or1k/tags/rel_3/or1200/
871 Generic flip-flop based memory macro for register file. lampret 8029d 19h /or1k/tags/rel_3/or1200/
870 Added defines for enabling generic FF based memory macro for register file. lampret 8029d 19h /or1k/tags/rel_3/or1200/
869 Added generic flip-flop based memory macro instantiation. lampret 8029d 19h /or1k/tags/rel_3/or1200/
795 Added a directive to ignore signed division variables that are only used in simulation. lampret 8100d 18h /or1k/tags/rel_3/or1200/
794 Added again just recently removed full_case directive lampret 8100d 18h /or1k/tags/rel_3/or1200/
791 Fixed some ports in instnatiations that were removed from the modules lampret 8100d 18h /or1k/tags/rel_3/or1200/
790 Changed comment about synopsys to _synopsys_ because synthesis was complaining about unknown directives lampret 8100d 19h /or1k/tags/rel_3/or1200/
788 Some of the warnings fixed. lampret 8100d 20h /or1k/tags/rel_3/or1200/
778 Added second type of Virtual Silicon two-port SRAM (for register file). Changed defines for VS STP RAMs. lampret 8101d 16h /or1k/tags/rel_3/or1200/
777 Changed define name from OR1200_MEM2REG_FAST to OR1200_IMPL_MEM2REG2 lampret 8101d 16h /or1k/tags/rel_3/or1200/
776 Updated defines. lampret 8101d 16h /or1k/tags/rel_3/or1200/
775 Optimized cache controller FSM. lampret 8101d 16h /or1k/tags/rel_3/or1200/
774 Removed old files. lampret 8101d 16h /or1k/tags/rel_3/or1200/
737 Added alternative for critical path in DU. lampret 8116d 10h /or1k/tags/rel_3/or1200/
736 Changed generation of SPR address. Now it is ORed from base and offset instead of a sum. lampret 8119d 10h /or1k/tags/rel_3/or1200/
735 Fixed async loop. Changed multiplier type for ASIC. lampret 8119d 10h /or1k/tags/rel_3/or1200/

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