OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_4/] [or1200/] - Rev 736

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
736 Changed generation of SPR address. Now it is ORed from base and offset instead of a sum. lampret 8147d 08h /or1k/tags/rel_4/or1200/
735 Fixed async loop. Changed multiplier type for ASIC. lampret 8147d 08h /or1k/tags/rel_4/or1200/
668 Lapsus fixed. simons 8171d 18h /or1k/tags/rel_4/or1200/
663 No longer using async rst as sync reset for the counter. lampret 8174d 08h /or1k/tags/rel_4/or1200/
660 Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr. lampret 8175d 05h /or1k/tags/rel_4/or1200/
636 Fixed combinational loops. lampret 8184d 13h /or1k/tags/rel_4/or1200/
617 Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways. lampret 8189d 08h /or1k/tags/rel_4/or1200/
610 Changed default reset values for SR and ESR to match or1ksim's. Fixed flop model in or1200_dpram_32x32 when OR1200_XILINX_RAM32X1D is defined. lampret 8194d 01h /or1k/tags/rel_4/or1200/
597 Fixed OR1200_XILINX_RAM32X1D. lampret 8197d 19h /or1k/tags/rel_4/or1200/
596 SR[TEE] should be zero after reset. lampret 8198d 00h /or1k/tags/rel_4/or1200/
595 Fixed 'the NPC single-step fix'. lampret 8198d 19h /or1k/tags/rel_4/or1200/
589 No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC. lampret 8199d 01h /or1k/tags/rel_4/or1200/
573 Fixed module name when compiling with OR1200_XILINX_RAM32X1D lampret 8202d 03h /or1k/tags/rel_4/or1200/
571 Changed alignment exception EPCR. Not tested yet. lampret 8202d 12h /or1k/tags/rel_4/or1200/
570 Fixed order of syscall and range exceptions. lampret 8202d 14h /or1k/tags/rel_4/or1200/
569 Default ASIC configuration does not sample WB inputs. lampret 8203d 00h /or1k/tags/rel_4/or1200/
562 Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if. lampret 8203d 03h /or1k/tags/rel_4/or1200/
536 Fixed typo. OR1200_REGISTERED_OUTPUTS was not defined. Should be. lampret 8209d 08h /or1k/tags/rel_4/or1200/
512 Uncommented OR1200_REGISTERED_OUTPUTS for FPGA target. lampret 8213d 12h /or1k/tags/rel_4/or1200/
504 New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs. lampret 8214d 01h /or1k/tags/rel_4/or1200/
402 Added OR1200_GENERIC_MULTP2_32X32 and OR1200_ASIC_MULTP2_32X32 lampret 8244d 04h /or1k/tags/rel_4/or1200/
401 *** empty log message *** simons 8247d 14h /or1k/tags/rel_4/or1200/
400 force_dslot_fetch does not work - allways zero. simons 8247d 14h /or1k/tags/rel_4/or1200/
399 Trap insn couses break after exits ex_insn. simons 8247d 14h /or1k/tags/rel_4/or1200/
391 Fixed except_stop width and fixed EX PC for 1400444f no-ops. lampret 8250d 10h /or1k/tags/rel_4/or1200/
390 Changed instantiation name of VS RAMs. lampret 8250d 12h /or1k/tags/rel_4/or1200/
387 Now FPGA and ASIC target are separate. lampret 8250d 14h /or1k/tags/rel_4/or1200/
386 Fixed VS RAM instantiation - again. lampret 8250d 14h /or1k/tags/rel_4/or1200/
370 Program counter divided to PPC and NPC. simons 8254d 12h /or1k/tags/rel_4/or1200/
367 Changed DSR/DRR behavior and exception detection. lampret 8255d 01h /or1k/tags/rel_4/or1200/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.