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[/] [or1k/] [tags/] [rel_4/] [or1200/] [rtl/] - Rev 617

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Rev Log message Author Age Path
617 Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways. lampret 8201d 03h /or1k/tags/rel_4/or1200/rtl/
610 Changed default reset values for SR and ESR to match or1ksim's. Fixed flop model in or1200_dpram_32x32 when OR1200_XILINX_RAM32X1D is defined. lampret 8205d 20h /or1k/tags/rel_4/or1200/rtl/
597 Fixed OR1200_XILINX_RAM32X1D. lampret 8209d 14h /or1k/tags/rel_4/or1200/rtl/
596 SR[TEE] should be zero after reset. lampret 8209d 19h /or1k/tags/rel_4/or1200/rtl/
595 Fixed 'the NPC single-step fix'. lampret 8210d 14h /or1k/tags/rel_4/or1200/rtl/
589 No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC. lampret 8210d 20h /or1k/tags/rel_4/or1200/rtl/
573 Fixed module name when compiling with OR1200_XILINX_RAM32X1D lampret 8213d 22h /or1k/tags/rel_4/or1200/rtl/
571 Changed alignment exception EPCR. Not tested yet. lampret 8214d 07h /or1k/tags/rel_4/or1200/rtl/
570 Fixed order of syscall and range exceptions. lampret 8214d 09h /or1k/tags/rel_4/or1200/rtl/
569 Default ASIC configuration does not sample WB inputs. lampret 8214d 18h /or1k/tags/rel_4/or1200/rtl/
562 Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if. lampret 8214d 22h /or1k/tags/rel_4/or1200/rtl/
536 Fixed typo. OR1200_REGISTERED_OUTPUTS was not defined. Should be. lampret 8221d 03h /or1k/tags/rel_4/or1200/rtl/
512 Uncommented OR1200_REGISTERED_OUTPUTS for FPGA target. lampret 8225d 07h /or1k/tags/rel_4/or1200/rtl/
504 New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs. lampret 8225d 20h /or1k/tags/rel_4/or1200/rtl/
402 Added OR1200_GENERIC_MULTP2_32X32 and OR1200_ASIC_MULTP2_32X32 lampret 8255d 23h /or1k/tags/rel_4/or1200/rtl/
401 *** empty log message *** simons 8259d 09h /or1k/tags/rel_4/or1200/rtl/
400 force_dslot_fetch does not work - allways zero. simons 8259d 09h /or1k/tags/rel_4/or1200/rtl/
399 Trap insn couses break after exits ex_insn. simons 8259d 09h /or1k/tags/rel_4/or1200/rtl/
391 Fixed except_stop width and fixed EX PC for 1400444f no-ops. lampret 8262d 05h /or1k/tags/rel_4/or1200/rtl/
390 Changed instantiation name of VS RAMs. lampret 8262d 07h /or1k/tags/rel_4/or1200/rtl/
387 Now FPGA and ASIC target are separate. lampret 8262d 08h /or1k/tags/rel_4/or1200/rtl/
386 Fixed VS RAM instantiation - again. lampret 8262d 08h /or1k/tags/rel_4/or1200/rtl/
370 Program counter divided to PPC and NPC. simons 8266d 06h /or1k/tags/rel_4/or1200/rtl/
367 Changed DSR/DRR behavior and exception detection. lampret 8266d 19h /or1k/tags/rel_4/or1200/rtl/
365 Added wb_cyc_o assignment after it was removed by accident. lampret 8267d 14h /or1k/tags/rel_4/or1200/rtl/
360 Added OR1200_REGISTERED_INPUTS. lampret 8269d 06h /or1k/tags/rel_4/or1200/rtl/
359 Added optional sampling of inputs. lampret 8269d 06h /or1k/tags/rel_4/or1200/rtl/
358 Fixed virtual silicon single-port rams instantiation. lampret 8269d 07h /or1k/tags/rel_4/or1200/rtl/
357 Fixed dbg_is_o assignment width. lampret 8269d 07h /or1k/tags/rel_4/or1200/rtl/
356 Break point bug fixed simons 8269d 09h /or1k/tags/rel_4/or1200/rtl/

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