OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_5/] - Rev 778

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
778 Added second type of Virtual Silicon two-port SRAM (for register file). Changed defines for VS STP RAMs. lampret 8131d 13h /or1k/tags/rel_5/
777 Changed define name from OR1200_MEM2REG_FAST to OR1200_IMPL_MEM2REG2 lampret 8131d 14h /or1k/tags/rel_5/
776 Updated defines. lampret 8131d 14h /or1k/tags/rel_5/
775 Optimized cache controller FSM. lampret 8131d 14h /or1k/tags/rel_5/
774 Removed old files. lampret 8131d 14h /or1k/tags/rel_5/
773 Changing directory structure ... lampret 8131d 15h /or1k/tags/rel_5/
772 Changing directory structure ... lampret 8131d 15h /or1k/tags/rel_5/
771 Added Makefile that is used to convert linux binary to loadable file for XSV board lampret 8132d 15h /or1k/tags/rel_5/
770 Maze application added. Mouse driver changed. simons 8133d 08h /or1k/tags/rel_5/
768 This commit was generated by cvs2svn to compensate for changes in r767,
which included commits to RCS files with non-trunk default branches.
lampret 8133d 12h /or1k/tags/rel_5/
766 Color bits position changed. simons 8133d 17h /or1k/tags/rel_5/
765 Kernel source files changed to enable allocation of blocks sizes above 1M. simons 8133d 19h /or1k/tags/rel_5/
764 Some further changes. simons 8133d 19h /or1k/tags/rel_5/
763 FTP and telnet working on or1ksim. simons 8134d 10h /or1k/tags/rel_5/
762 Mistake fixed. simons 8137d 23h /or1k/tags/rel_5/
761 Checksum calculation fixed. simons 8138d 00h /or1k/tags/rel_5/
760 Fixed defines for running on XSV800 at 10MHz lampret 8138d 11h /or1k/tags/rel_5/
759 Explained 10MHz. Fixed directory name. lampret 8138d 11h /or1k/tags/rel_5/
758 Fixed relative/absolute paths. Changed soem file names. lampret 8138d 11h /or1k/tags/rel_5/
757 Removed or1ksim binary. Properly is to compile it and install it. lampret 8138d 11h /or1k/tags/rel_5/
756 Changed clock from 12.5MHz to 10MHz. lampret 8138d 11h /or1k/tags/rel_5/
755 This commit was generated by cvs2svn to compensate for changes in r754,
which included commits to RCS files with non-trunk default branches.
lampret 8138d 12h /or1k/tags/rel_5/
753 Memory map and interrupt settings changed to fit new hw. simons 8138d 13h /or1k/tags/rel_5/
752 Fixed some typos lampret 8138d 15h /or1k/tags/rel_5/
751 This commit was generated by cvs2svn to compensate for changes in r750,
which included commits to RCS files with non-trunk default branches.
lampret 8138d 15h /or1k/tags/rel_5/
749 This commit was generated by cvs2svn to compensate for changes in r748,
which included commits to RCS files with non-trunk default branches.
lampret 8138d 16h /or1k/tags/rel_5/
747 First import of the "new" XESS XSV environment. lampret 8138d 16h /or1k/tags/rel_5/
746 First import of the "new" XESS XSV environment. lampret 8138d 16h /or1k/tags/rel_5/
745 ifconfig route and ping tested on or1ksim. simons 8142d 13h /or1k/tags/rel_5/
744 Some changes and fixes. simons 8142d 13h /or1k/tags/rel_5/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.