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[/] [or1k/] [tags/] [rel_5/] [or1200/] - Rev 610

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Rev Log message Author Age Path
610 Changed default reset values for SR and ESR to match or1ksim's. Fixed flop model in or1200_dpram_32x32 when OR1200_XILINX_RAM32X1D is defined. lampret 8198d 10h /or1k/tags/rel_5/or1200/
597 Fixed OR1200_XILINX_RAM32X1D. lampret 8202d 04h /or1k/tags/rel_5/or1200/
596 SR[TEE] should be zero after reset. lampret 8202d 08h /or1k/tags/rel_5/or1200/
595 Fixed 'the NPC single-step fix'. lampret 8203d 04h /or1k/tags/rel_5/or1200/
589 No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC. lampret 8203d 10h /or1k/tags/rel_5/or1200/
573 Fixed module name when compiling with OR1200_XILINX_RAM32X1D lampret 8206d 12h /or1k/tags/rel_5/or1200/
571 Changed alignment exception EPCR. Not tested yet. lampret 8206d 21h /or1k/tags/rel_5/or1200/
570 Fixed order of syscall and range exceptions. lampret 8206d 23h /or1k/tags/rel_5/or1200/
569 Default ASIC configuration does not sample WB inputs. lampret 8207d 08h /or1k/tags/rel_5/or1200/
562 Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if. lampret 8207d 12h /or1k/tags/rel_5/or1200/
536 Fixed typo. OR1200_REGISTERED_OUTPUTS was not defined. Should be. lampret 8213d 17h /or1k/tags/rel_5/or1200/
512 Uncommented OR1200_REGISTERED_OUTPUTS for FPGA target. lampret 8217d 20h /or1k/tags/rel_5/or1200/
504 New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs. lampret 8218d 10h /or1k/tags/rel_5/or1200/
402 Added OR1200_GENERIC_MULTP2_32X32 and OR1200_ASIC_MULTP2_32X32 lampret 8248d 13h /or1k/tags/rel_5/or1200/
401 *** empty log message *** simons 8251d 23h /or1k/tags/rel_5/or1200/
400 force_dslot_fetch does not work - allways zero. simons 8251d 23h /or1k/tags/rel_5/or1200/
399 Trap insn couses break after exits ex_insn. simons 8251d 23h /or1k/tags/rel_5/or1200/
391 Fixed except_stop width and fixed EX PC for 1400444f no-ops. lampret 8254d 19h /or1k/tags/rel_5/or1200/
390 Changed instantiation name of VS RAMs. lampret 8254d 20h /or1k/tags/rel_5/or1200/
387 Now FPGA and ASIC target are separate. lampret 8254d 22h /or1k/tags/rel_5/or1200/
386 Fixed VS RAM instantiation - again. lampret 8254d 22h /or1k/tags/rel_5/or1200/
370 Program counter divided to PPC and NPC. simons 8258d 20h /or1k/tags/rel_5/or1200/
367 Changed DSR/DRR behavior and exception detection. lampret 8259d 09h /or1k/tags/rel_5/or1200/
365 Added wb_cyc_o assignment after it was removed by accident. lampret 8260d 04h /or1k/tags/rel_5/or1200/
360 Added OR1200_REGISTERED_INPUTS. lampret 8261d 20h /or1k/tags/rel_5/or1200/
359 Added optional sampling of inputs. lampret 8261d 20h /or1k/tags/rel_5/or1200/
358 Fixed virtual silicon single-port rams instantiation. lampret 8261d 20h /or1k/tags/rel_5/or1200/
357 Fixed dbg_is_o assignment width. lampret 8261d 20h /or1k/tags/rel_5/or1200/
356 Break point bug fixed simons 8261d 23h /or1k/tags/rel_5/or1200/
354 Fixed width of du_except. lampret 8262d 17h /or1k/tags/rel_5/or1200/

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