OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_6/] - Rev 1033

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
1033 If SR[CY] implemented with OR1200_IMPL_ADDC enabled, l.add/l.addi also set SR[CY]. lampret 8004d 09h /or1k/tags/rel_6/
1032 Added optional SR[CY]. Added define to enable additional (compare) flag modifiers. Defines are OR1200_IMPL_ADDC and OR1200_ADDITIONAL_FLAG_MODIFIERS. lampret 8004d 23h /or1k/tags/rel_6/
1031 Setting phy to 10Mbps full duplex. simons 8005d 14h /or1k/tags/rel_6/
1030 Ethernet configured for 10Mbps. simons 8006d 11h /or1k/tags/rel_6/
1029 Typing error fixed. simons 8006d 11h /or1k/tags/rel_6/
1028 Import. ivang 8006d 11h /or1k/tags/rel_6/
1027 PRINTF/printf mess fixed. simons 8006d 20h /or1k/tags/rel_6/
1026 rtems-20020807 import ivang 8007d 05h /or1k/tags/rel_6/
1025 PRINTF/printf mess fixed. simons 8007d 09h /or1k/tags/rel_6/
1024 Mess with printf/PRINTF fixed. Ethernet test changed to support latest changes. simons 8007d 17h /or1k/tags/rel_6/
1023 Now most of the configuration registers are updatded automatically based on defines in or1200_defines.v. lampret 8008d 04h /or1k/tags/rel_6/
1022 As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy. lampret 8008d 06h /or1k/tags/rel_6/
1021 *** empty log message *** rherveille 8012d 09h /or1k/tags/rel_6/
1020 Fixed several bugs
Working version, tested on Bender hardware		 rherveille 8012d 09h /or1k/tags/rel_6/
1019 fixed some bugs detected by Bender hardware rherveille 8012d 09h /or1k/tags/rel_6/
1018 TX_BD_NUM register now contains a real number of transmit BDs (before this was n*2) simons 8012d 16h /or1k/tags/rel_6/
1017 TX_BD_NUM register now contains a real number of transmit BDs (before this was n*2) simons 8012d 16h /or1k/tags/rel_6/
1016 64 bytes is the smallest packet size. simons 8013d 08h /or1k/tags/rel_6/
1015 Host type was not recognized. simons 8013d 18h /or1k/tags/rel_6/
1014 added _JBLEN definition for or1k ivang 8014d 08h /or1k/tags/rel_6/
1013 ORP architecture supported. simons 8014d 10h /or1k/tags/rel_6/
1011 Removed some commented RTL. Fixed SR/ESR flag bug. lampret 8015d 03h /or1k/tags/rel_6/
1010 Import ivang 8019d 06h /or1k/tags/rel_6/
1009 Import ivang 8019d 07h /or1k/tags/rel_6/
1008 Import ivang 8019d 07h /or1k/tags/rel_6/
1007 Import ivang 8019d 07h /or1k/tags/rel_6/
1006 Import ivang 8019d 07h /or1k/tags/rel_6/
1005 Import ivang 8019d 07h /or1k/tags/rel_6/
1004 Now every ramdisk image should have init program. simons 8019d 16h /or1k/tags/rel_6/
1003 cuc temporary files are deleted upon exiting markom 8019d 16h /or1k/tags/rel_6/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.