OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_7/] - Rev 88

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
88 Update. lampret 8502d 07h /or1k/tags/rel_7/
87 Files required for creation of html files. lampret 8502d 07h /or1k/tags/rel_7/
86 Added dh command. lampret 8502d 08h /or1k/tags/rel_7/
85 Added dumphex. lampret 8502d 08h /or1k/tags/rel_7/
84 Update. lampret 8502d 08h /or1k/tags/rel_7/
83 Updates. lampret 8502d 08h /or1k/tags/rel_7/
82 Changed pctemp to pcnext. lampret 8502d 08h /or1k/tags/rel_7/
80 First import. lampret 8530d 02h /or1k/tags/rel_7/
79 Data and instruction cache simulation added. lampret 8531d 23h /or1k/tags/rel_7/
78 (i/d)tlb_status lampret 8655d 13h /or1k/tags/rel_7/
77 Regular update. lampret 8655d 13h /or1k/tags/rel_7/
76 regular update lampret 8655d 13h /or1k/tags/rel_7/
75 simgetstr added. eval_mem32 replaced with evalsim_mem32. lampret 8655d 13h /or1k/tags/rel_7/
74 Same as DMMU. lampret 8662d 13h /or1k/tags/rel_7/
73 Fixed all bugs. Now more or less works. IMMU still has some problems (exception start). lampret 8662d 13h /or1k/tags/rel_7/
72 Added 'how to build GNU tools' lampret 8667d 14h /or1k/tags/rel_7/
71 Clean two typos. lampret 8672d 15h /or1k/tags/rel_7/
70 Basic setjmp/longjmp are ready. lampret 8672d 15h /or1k/tags/rel_7/
69 Sim debug. lampret 8674d 13h /or1k/tags/rel_7/
68 Added hook for l.sys 204. Changed SPR of flag (no more CCR) lampret 8674d 13h /or1k/tags/rel_7/
67 Added simulator "application load". lampret 8674d 13h /or1k/tags/rel_7/
66 Added another set of eval_ functions that should be used directly by simulator.
evalsim_ and setsim_ don't go through MMU transaltion mechanism.		 lampret 8674d 13h /or1k/tags/rel_7/
65 Added DMMU stats. lampret 8674d 13h /or1k/tags/rel_7/
64 SPR bit definition moved to spr_defs.h. lampret 8674d 13h /or1k/tags/rel_7/
63 Fixed a bug in getsprbits/setsprbits functions (now mask can have arbitry
alignment of bits).		 lampret 8674d 13h /or1k/tags/rel_7/
62 OR1K DMMU model. lampret 8674d 13h /or1k/tags/rel_7/
61 2000-09-26 Joel Sherrill <joel@OARcorp.com>

* libc/sys/rtems/include/pthread.h: Added file missed by earlier
commit of RTEMS modifications.		 joel 8689d 08h /or1k/tags/rel_7/
60 Memory model changed. lampret 8709d 17h /or1k/tags/rel_7/
59 2000-09-05 Joel Sherrill <joel@OARcorp.com>

* Merged newlib-1.8.2-rtems-20000905.diff which includes
or16 and or32 configuration support.		 joel 8710d 04h /or1k/tags/rel_7/
57 This commit was generated by cvs2svn to compensate for changes in r56, which
included commits to RCS files with non-trunk default branches.		 joel 8716d 02h /or1k/tags/rel_7/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.