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[/] [or1k/] [tags/] [rel_8/] [or1200/] [rtl/] - Rev 994

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Rev Log message Author Age Path
994 Store buffer has been tested and it works. BY default it is still disabled until uClinux confirms correct operation on FPGA board. lampret 7982d 01h /or1k/tags/rel_8/or1200/rtl/
993 Fixed IMMU bug. lampret 7982d 01h /or1k/tags/rel_8/or1200/rtl/
984 Disable SB until it is tested lampret 7985d 05h /or1k/tags/rel_8/or1200/rtl/
977 Added store buffer. lampret 7985d 07h /or1k/tags/rel_8/or1200/rtl/
962 Fixed Xilinx trace buffer address. REported by Taylor Su. lampret 7988d 21h /or1k/tags/rel_8/or1200/rtl/
958 Disabled ITLB translation when 1) doing access to ITLB SPRs or 2) crossing page. This modification was tested only with parts of IMMU test - remaining test cases needs to be run. lampret 7989d 21h /or1k/tags/rel_8/or1200/rtl/
944 Added OR1200_WB_RETRY. Moved WB registered outsputs / samples inputs into lower section. lampret 7991d 22h /or1k/tags/rel_8/or1200/rtl/
943 Added optional retry counter for wb_rty_i. Added graceful termination for aborted transfers. lampret 7991d 22h /or1k/tags/rel_8/or1200/rtl/
942 Delayed external access at page crossing. lampret 7991d 22h /or1k/tags/rel_8/or1200/rtl/
916 MAC now follows software convention (signed multiply instead of unsigned). lampret 8004d 01h /or1k/tags/rel_8/or1200/rtl/
895 Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized. lampret 8020d 05h /or1k/tags/rel_8/or1200/rtl/
871 Generic flip-flop based memory macro for register file. lampret 8056d 11h /or1k/tags/rel_8/or1200/rtl/
870 Added defines for enabling generic FF based memory macro for register file. lampret 8056d 11h /or1k/tags/rel_8/or1200/rtl/
869 Added generic flip-flop based memory macro instantiation. lampret 8056d 11h /or1k/tags/rel_8/or1200/rtl/
795 Added a directive to ignore signed division variables that are only used in simulation. lampret 8127d 11h /or1k/tags/rel_8/or1200/rtl/
794 Added again just recently removed full_case directive lampret 8127d 11h /or1k/tags/rel_8/or1200/rtl/
791 Fixed some ports in instnatiations that were removed from the modules lampret 8127d 11h /or1k/tags/rel_8/or1200/rtl/
790 Changed comment about synopsys to _synopsys_ because synthesis was complaining about unknown directives lampret 8127d 11h /or1k/tags/rel_8/or1200/rtl/
788 Some of the warnings fixed. lampret 8127d 12h /or1k/tags/rel_8/or1200/rtl/
778 Added second type of Virtual Silicon two-port SRAM (for register file). Changed defines for VS STP RAMs. lampret 8128d 08h /or1k/tags/rel_8/or1200/rtl/
777 Changed define name from OR1200_MEM2REG_FAST to OR1200_IMPL_MEM2REG2 lampret 8128d 08h /or1k/tags/rel_8/or1200/rtl/
776 Updated defines. lampret 8128d 08h /or1k/tags/rel_8/or1200/rtl/
775 Optimized cache controller FSM. lampret 8128d 08h /or1k/tags/rel_8/or1200/rtl/
774 Removed old files. lampret 8128d 08h /or1k/tags/rel_8/or1200/rtl/
737 Added alternative for critical path in DU. lampret 8143d 03h /or1k/tags/rel_8/or1200/rtl/
736 Changed generation of SPR address. Now it is ORed from base and offset instead of a sum. lampret 8146d 02h /or1k/tags/rel_8/or1200/rtl/
735 Fixed async loop. Changed multiplier type for ASIC. lampret 8146d 02h /or1k/tags/rel_8/or1200/rtl/
668 Lapsus fixed. simons 8170d 12h /or1k/tags/rel_8/or1200/rtl/
663 No longer using async rst as sync reset for the counter. lampret 8173d 02h /or1k/tags/rel_8/or1200/rtl/
660 Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr. lampret 8173d 23h /or1k/tags/rel_8/or1200/rtl/

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