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Rev Log message Author Age Path
415 DTLB test tested on simulator. simons 8255d 22h /or1k/tags/rel_9/
414 Stack section should not be loaded into mamory. simons 8256d 06h /or1k/tags/rel_9/
413 some section changes markom 8256d 07h /or1k/tags/rel_9/
412 *** empty log message *** simons 8256d 08h /or1k/tags/rel_9/
411 acv uart testsuite now works (without modem test) markom 8256d 11h /or1k/tags/rel_9/
410 MMU test added. simons 8257d 05h /or1k/tags/rel_9/
409 some minor changes to or1ksim; Testbench except.s modified. Interrupt test almost finished for uart ACV. markom 8257d 11h /or1k/tags/rel_9/
408 Fixed errant rx_bd_num erez 8258d 07h /or1k/tags/rel_9/
406 Renamed ethernet's RX_BD_ADR to RX_BD_NUM erez 8258d 10h /or1k/tags/rel_9/
405 Stepping trough l.jal and l.jalr fixed. simons 8259d 11h /or1k/tags/rel_9/
404 is_delayed() is used outside this file. simons 8259d 11h /or1k/tags/rel_9/
403 Prompt changed because ddd requires (gdb). simons 8259d 11h /or1k/tags/rel_9/
402 Added OR1200_GENERIC_MULTP2_32X32 and OR1200_ASIC_MULTP2_32X32 lampret 8259d 16h /or1k/tags/rel_9/
401 *** empty log message *** simons 8263d 02h /or1k/tags/rel_9/
400 force_dslot_fetch does not work - allways zero. simons 8263d 02h /or1k/tags/rel_9/
399 Trap insn couses break after exits ex_insn. simons 8263d 02h /or1k/tags/rel_9/
398 added register field defines ivang 8265d 07h /or1k/tags/rel_9/
397 removed or16 architecture markom 8265d 08h /or1k/tags/rel_9/
396 added missing file markom 8265d 10h /or1k/tags/rel_9/
395 removed obsolete dependency and history from cpu section markom 8265d 12h /or1k/tags/rel_9/
394 dependency joined with dependstats; history moved to sim section markom 8265d 14h /or1k/tags/rel_9/
393 messages: exception on many places changed to abort markom 8265d 14h /or1k/tags/rel_9/
391 Fixed except_stop width and fixed EX PC for 1400444f no-ops. lampret 8265d 22h /or1k/tags/rel_9/
390 Changed instantiation name of VS RAMs. lampret 8265d 23h /or1k/tags/rel_9/
389 Changed default delay for load and store in superscalar cpu. lampret 8266d 00h /or1k/tags/rel_9/
388 Added comments for cpu section. lampret 8266d 00h /or1k/tags/rel_9/
387 Now FPGA and ASIC target are separate. lampret 8266d 01h /or1k/tags/rel_9/
386 Fixed VS RAM instantiation - again. lampret 8266d 01h /or1k/tags/rel_9/
385 check testbench now modified to work with new report output markom 8266d 07h /or1k/tags/rel_9/
384 modified simmem.cfg structure! ADD > BEFORE EACH LINE! markom 8266d 08h /or1k/tags/rel_9/

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