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[/] [or1k/] [tags/] [stable_0_1_0/] [or1ksim/] - Rev 131

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Rev Log message Author Age Path
131 Initial checkin of the Debug Unit register descriptions chris 8429d 19h /or1k/tags/stable_0_1_0/or1ksim/
130 Initial checkin of the debug unit module chris 8429d 19h /or1k/tags/stable_0_1_0/or1ksim/
129 Added code to inject insn from Debug Unit DIR chris 8429d 19h /or1k/tags/stable_0_1_0/or1ksim/
128 Added code to check debug unit after an exception chris 8429d 19h /or1k/tags/stable_0_1_0/or1ksim/
127 Added GDB debugging protocol. chris 8429d 19h /or1k/tags/stable_0_1_0/or1ksim/
123 Bugs fixed:
- l.rfe temporarly disables exceptions
- l.sys does PC -= 4
- breakpoints now supported at peripheria locations
- uart0.rt/.tx nonexistent file segment fault

Other modifications:
- replaced string names to instruction indexes
- execute.c executes specified (in ISA table) function
- modified ISA table - flag needed for gdb
- added or32.c, which supports or32.h
- added new instructions l.mac, l.msb, l.maci, l.macrc
and their executing functions (opcodes to be revisited)
- added header acconfig.h
- modified configuration files		 markom 8435d 17h /or1k/tags/stable_0_1_0/or1ksim/
110 bug fix. markom 8456d 19h /or1k/tags/stable_0_1_0/or1ksim/
103 Major update to include PM, PIC, Cache Mngmnt and non-interactive mode. lampret 8461d 01h /or1k/tags/stable_0_1_0/or1ksim/
102 Major update to include PM, PIC, Cache Mngmnt and non-interactive mode. lampret 8461d 02h /or1k/tags/stable_0_1_0/or1ksim/
100 Updated tick facility. lampret 8476d 02h /or1k/tags/stable_0_1_0/or1ksim/
99 *** empty log message *** lampret 8476d 02h /or1k/tags/stable_0_1_0/or1ksim/
98 Return value register is now r9. lampret 8476d 02h /or1k/tags/stable_0_1_0/or1ksim/
97 Description of all test cases (at least working one). lampret 8476d 02h /or1k/tags/stable_0_1_0/or1ksim/
94 Update. lampret 8506d 05h /or1k/tags/stable_0_1_0/or1ksim/
93 Adding uos. lampret 8506d 05h /or1k/tags/stable_0_1_0/or1ksim/
92 Tick timer. lampret 8506d 08h /or1k/tags/stable_0_1_0/or1ksim/
91 Tick timer facility. lampret 8506d 08h /or1k/tags/stable_0_1_0/or1ksim/
90 Added tick timer. lampret 8506d 10h /or1k/tags/stable_0_1_0/or1ksim/
86 Added dh command. lampret 8507d 17h /or1k/tags/stable_0_1_0/or1ksim/
85 Added dumphex. lampret 8507d 17h /or1k/tags/stable_0_1_0/or1ksim/
84 Update. lampret 8507d 17h /or1k/tags/stable_0_1_0/or1ksim/
83 Updates. lampret 8507d 17h /or1k/tags/stable_0_1_0/or1ksim/
82 Changed pctemp to pcnext. lampret 8507d 17h /or1k/tags/stable_0_1_0/or1ksim/
79 Data and instruction cache simulation added. lampret 8537d 09h /or1k/tags/stable_0_1_0/or1ksim/
78 (i/d)tlb_status lampret 8660d 23h /or1k/tags/stable_0_1_0/or1ksim/
77 Regular update. lampret 8660d 23h /or1k/tags/stable_0_1_0/or1ksim/
76 regular update lampret 8660d 23h /or1k/tags/stable_0_1_0/or1ksim/
75 simgetstr added. eval_mem32 replaced with evalsim_mem32. lampret 8660d 23h /or1k/tags/stable_0_1_0/or1ksim/
74 Same as DMMU. lampret 8667d 22h /or1k/tags/stable_0_1_0/or1ksim/
73 Fixed all bugs. Now more or less works. IMMU still has some problems (exception start). lampret 8667d 22h /or1k/tags/stable_0_1_0/or1ksim/

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