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[/] [or1k/] [tags/] [stable_0_1_0/] [or1ksim/] - Rev 26

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Rev Log message Author Age Path
26 Clean up. lampret 8816d 04h /or1k/tags/stable_0_1_0/or1ksim/
25 Bug fix in handling labels when loading code into simulator memory. lampret 8816d 04h /or1k/tags/stable_0_1_0/or1ksim/
24 Static branch prediction added. lampret 8816d 04h /or1k/tags/stable_0_1_0/or1ksim/
23 Common OR1K backend for OR32 and OR16. lampret 8816d 04h /or1k/tags/stable_0_1_0/or1ksim/
22 More modifications related to or16. lampret 8818d 10h /or1k/tags/stable_0_1_0/or1ksim/
21 More modifications related to or16. cmchen 8818d 10h /or1k/tags/stable_0_1_0/or1ksim/
20 or1k renamed to or32. lampret 8818d 23h /or1k/tags/stable_0_1_0/or1ksim/
19 Added or16, or1k renamed to or32. lampret 8818d 23h /or1k/tags/stable_0_1_0/or1ksim/
18 or16 added, or1k renamed to or32. lampret 8819d 00h /or1k/tags/stable_0_1_0/or1ksim/
17 Re-generated. jrydberg 8841d 20h /or1k/tags/stable_0_1_0/or1ksim/
16 Add support for systems without readline. To use GNU readline library,
use the `--enable-readline' option to the configure script.		 jrydberg 8841d 20h /or1k/tags/stable_0_1_0/or1ksim/
15 Initial revision. jrydberg 8878d 10h /or1k/tags/stable_0_1_0/or1ksim/
13 Rebuild of the generated files. jrydberg 8879d 16h /or1k/tags/stable_0_1_0/or1ksim/
12 Added information to the section about how to configure and compile
the package.		 jrydberg 8879d 16h /or1k/tags/stable_0_1_0/or1ksim/
11 Rebuild from configure.in. jrydberg 8879d 16h /or1k/tags/stable_0_1_0/or1ksim/
10 Support for both architectures. Specify architecture with the
--target option.		 jrydberg 8879d 16h /or1k/tags/stable_0_1_0/or1ksim/
9 Added support for OpenRISC 100 and DLX. jrydberg 8879d 16h /or1k/tags/stable_0_1_0/or1ksim/
8 Initial revision. jrydberg 8879d 16h /or1k/tags/stable_0_1_0/or1ksim/
7 Major update of the enviorment. Now uses autoconf and automake. The
simulator uses readline aswell to get input from the user. A number of
new files added, some modified. The libc directory is now called support.		 jrydberg 8879d 16h /or1k/tags/stable_0_1_0/or1ksim/
6 Just a regular update with exception of cache simulation. MMU simulation still under development. lampret 8880d 10h /or1k/tags/stable_0_1_0/or1ksim/
5 Data and instruction cache simulation added. lampret 8880d 10h /or1k/tags/stable_0_1_0/or1ksim/
4 no message lampret 8930d 14h /or1k/tags/stable_0_1_0/or1ksim/
3 This commit was generated by cvs2svn to compensate for changes in r2, which
included commits to RCS files with non-trunk default branches.		 cvs 9006d 04h /or1k/tags/stable_0_1_0/or1ksim/

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