Rev |
Log message |
Author |
Age |
Path |
1165 |
timeout bug fixed; contribution by Carlos |
markom |
7705d 11h |
/or1k/tags/stable_0_2_0/ |
1161 |
When OR1200_NO_IMMU and OR1200_NO_IC are not both defined or undefined at the same time, results in a IC bug. Fixed. |
lampret |
7708d 23h |
/or1k/tags/stable_0_2_0/ |
1160 |
added missing .rodata.* section into rom linker script |
phoenix |
7740d 00h |
/or1k/tags/stable_0_2_0/ |
1159 |
No functional changes. Added defines to disable implementation of multiplier/MAC |
lampret |
7752d 02h |
/or1k/tags/stable_0_2_0/ |
1158 |
Added simple uart test case. |
lampret |
7753d 04h |
/or1k/tags/stable_0_2_0/ |
1157 |
Added syscall test case. |
lampret |
7753d 04h |
/or1k/tags/stable_0_2_0/ |
1156 |
Tick timer test case added. |
lampret |
7754d 00h |
/or1k/tags/stable_0_2_0/ |
1155 |
No functional change. Only added customization for exception vectors. |
lampret |
7755d 04h |
/or1k/tags/stable_0_2_0/ |
1154 |
When using tty channel, put the serial port into raw mode (no echo, no
CR/LF conversion, no other line discipline/buffering). |
sfurman |
7762d 19h |
/or1k/tags/stable_0_2_0/ |
1153 |
When multiple interrupts were pending, e.g. TX buffer empty and RX
available, reading the UART's IIR register could potentially clear a
TX interrupt before it had been sent to the processor, thus dropping
the interrupt permanently.
Fix tested w/ both eCos and uclinux. |
sfurman |
7763d 06h |
/or1k/tags/stable_0_2_0/ |
1152 |
*** empty log message *** |
phoenix |
7763d 10h |
/or1k/tags/stable_0_2_0/ |
1151 |
*** empty log message *** |
phoenix |
7763d 10h |
/or1k/tags/stable_0_2_0/ |
1150 |
remove unneded include |
phoenix |
7763d 12h |
/or1k/tags/stable_0_2_0/ |
1149 |
*** empty log message *** |
phoenix |
7763d 23h |
/or1k/tags/stable_0_2_0/ |
1148 |
*** empty log message *** |
phoenix |
7763d 23h |
/or1k/tags/stable_0_2_0/ |
1147 |
remove unneeded include |
phoenix |
7763d 23h |
/or1k/tags/stable_0_2_0/ |
1146 |
cygwin fix |
phoenix |
7763d 23h |
/or1k/tags/stable_0_2_0/ |
1145 |
1) Fix trivial bug w/ transmitter empty interrupts that I introduced in the
last check-in.
2) Improve printed output from debugging-only uart_status() routine. |
sfurman |
7764d 00h |
/or1k/tags/stable_0_2_0/ |
1144 |
Speed up gdb when running with serial targets:
When generating backtraces, the prologue of each function is scanned
at least three times by architecture-independent code, e.g. to
determine offsets of saved registers, identify frameless functions,
etc. This new code adds straightforward caching of the information
gleaned by or1k_scan_prologue() on a per-frame basis rather than
storing it in global static variables. (This benefits both JTAG and
serial gdb targets, though the JTAG target runs fast enough that it is
not particularly needed.)
When the register set is dumped by the serial target, e.g. at any
breakpoint or interrupt, the 32 vector/FP registers were included in
the dump (each 8 bytes long), though they aren't implemented. The new
code tells gdb that unimplemented registers have zero length in the
dump. |
sfurman |
7766d 06h |
/or1k/tags/stable_0_2_0/ |
1143 |
Make UART transmitter-empty interrupts match both 16450 and 16550 behavior. |
sfurman |
7766d 20h |
/or1k/tags/stable_0_2_0/ |
1142 |
Speed up gdb when running with serial targets:
When generating backtraces, the prologue of each function is scanned
at least three times by architecture-independent code, e.g. to
determine offsets of saved registers, identify frameless functions,
etc. This new code adds straightforward caching of the information
gleaned by or1k_scan_prologue() on a per-frame basis rather than
storing it in global static variables. (This benefits both JTAG and
serial gdb targets, though the JTAG target runs fast enough that it is
not particularly needed.)
When the register set is dumped by the serial target, e.g. at any
breakpoint or interrupt, the 32 vector/FP registers were included in
the dump (each 8 bytes long), though they aren't implemented. The new
code tells gdb that unimplemented registers have zero length in the
dump. |
sfurman |
7766d 20h |
/or1k/tags/stable_0_2_0/ |
1141 |
WB = 1/2 RISC clock test code enabled. |
lampret |
7768d 05h |
/or1k/tags/stable_0_2_0/ |
1140 |
Fixed OR1200_CLKDIV_x_SUPPORTED defines. Fixed order of ifdefs. |
lampret |
7768d 05h |
/or1k/tags/stable_0_2_0/ |
1139 |
Fixed OR1200_CLKDIV_x_SUPPORTED defines. Better description. |
lampret |
7768d 05h |
/or1k/tags/stable_0_2_0/ |
1138 |
Added some information how to run simulations. |
lampret |
7769d 01h |
/or1k/tags/stable_0_2_0/ |
1137 |
Added RFRAM generic and Altera lpm library. |
lampret |
7769d 01h |
/or1k/tags/stable_0_2_0/ |
1136 |
Add altera lpm library. |
lampret |
7769d 01h |
/or1k/tags/stable_0_2_0/ |
1135 |
Added get_gpr support for OR1200_RFRAM_GENERIC |
lampret |
7769d 01h |
/or1k/tags/stable_0_2_0/ |
1134 |
Changed location of debug test code to 0. |
lampret |
7769d 01h |
/or1k/tags/stable_0_2_0/ |
1133 |
Adding OR1200_CLMODE_1TO2 test code. |
lampret |
7769d 01h |
/or1k/tags/stable_0_2_0/ |