OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [stable_0_2_0/] - Rev 1207

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
1207 Static exception prefix. lampret 7529d 10h /or1k/tags/stable_0_2_0/
1205 fix for gdb_debug config phoenix 7535d 19h /or1k/tags/stable_0_2_0/
1204 added additional field into executed log wich besides EA also prints PA (physical address) phoenix 7553d 07h /or1k/tags/stable_0_2_0/
1203 value stored in ITLB and DTLB match registers was wrong. fixed. phoenix 7553d 07h /or1k/tags/stable_0_2_0/
1202 at exception print insn number to ease debugging phoenix 7553d 07h /or1k/tags/stable_0_2_0/
1200 mbist signals updated according to newest convention markom 7578d 02h /or1k/tags/stable_0_2_0/
1199 Daniel Wiklund: Removed multiple entries of debug/Makefile in configure danwi 7582d 03h /or1k/tags/stable_0_2_0/
1198 make it compile on RH 8,9 phoenix 7607d 18h /or1k/tags/stable_0_2_0/
1197 disabled ram-init of ps2 (old) +
changed MAC type into DOS type, so that Xilinx ISE can work with it		 dries 7612d 23h /or1k/tags/stable_0_2_0/
1196 removed second debug/Makefile (credits: Daniel Wiklund - danwi@isy.liu.se) dries 7613d 00h /or1k/tags/stable_0_2_0/
1195 made the project file a little bit more universal dries 7613d 01h /or1k/tags/stable_0_2_0/
1194 correct all the syntax errors dries 7613d 01h /or1k/tags/stable_0_2_0/
1193 disabled SRAM_GENERIC and added comment +
corrected 'wb_err' into 'wb_err_o'		 dries 7613d 01h /or1k/tags/stable_0_2_0/
1192 disabled 'bench_defines.v' during synthesis +
added define to specify usage of flash instruction address		 dries 7613d 03h /or1k/tags/stable_0_2_0/
1191 disabled 'bench_defines.v' during synthesis +
added define to specify usage of flash instruction address		 dries 7613d 03h /or1k/tags/stable_0_2_0/
1188 Added support for rams with byte write access. simons 7629d 02h /or1k/tags/stable_0_2_0/
1186 Added support for rams with byte write access. simons 7630d 01h /or1k/tags/stable_0_2_0/
1184 Scan signals mess fixed. simons 7636d 18h /or1k/tags/stable_0_2_0/
1183 OpenRISC port of gdb-5.3 straightforwardly derived from gdb-5.0 sfurman 7641d 09h /or1k/tags/stable_0_2_0/
1181 Initial import of unmodified gdb-5.3 source on vendor branch sfurman 7641d 11h /or1k/tags/stable_0_2_0/
1179 BIST interface added for Artisan memory instances. simons 7644d 21h /or1k/tags/stable_0_2_0/
1178 avoid another immu exception that should not happen phoenix 7674d 08h /or1k/tags/stable_0_2_0/
1177 more informative output phoenix 7675d 15h /or1k/tags/stable_0_2_0/
1176 Added comments. damonb 7676d 06h /or1k/tags/stable_0_2_0/
1174 fix for immu exceptions that never should have happened phoenix 7677d 10h /or1k/tags/stable_0_2_0/
1170 Added support for l.addc instruction. csanchez 7685d 14h /or1k/tags/stable_0_2_0/
1169 Added support for l.addc instruction. csanchez 7685d 15h /or1k/tags/stable_0_2_0/
1168 Added explicit alignment expressions. csanchez 7691d 01h /or1k/tags/stable_0_2_0/
1167 Corrected offset of TSS field within task_struct. csanchez 7691d 01h /or1k/tags/stable_0_2_0/
1166 Fixed problem with relocations of non-allocated sections. csanchez 7691d 01h /or1k/tags/stable_0_2_0/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.