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[/] [or1k/] [tags/] [stable_0_2_0/] - Rev 1634

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Rev Log message Author Age Path
1634 First Import of RC20x uClinux jcastillo 6810d 15h /or1k/tags/stable_0_2_0/
1633 First Import of RC20x uClinux jcastillo 6810d 15h /or1k/tags/stable_0_2_0/
1632 First Import of RC20x uClinux jcastillo 6810d 15h /or1k/tags/stable_0_2_0/
1631 First Import jcastillo 6810d 15h /or1k/tags/stable_0_2_0/
1630 *** empty log message *** jcastillo 6810d 15h /or1k/tags/stable_0_2_0/
1629 First Import of uClinux for RC20x board jcastillo 6810d 16h /or1k/tags/stable_0_2_0/
1628 First Import of uClinux for RC20x board jcastillo 6810d 16h /or1k/tags/stable_0_2_0/
1627 First Import of RC20x uClinux jcastillo 6810d 16h /or1k/tags/stable_0_2_0/
1626 First Import of uClinux for RC20x board jcastillo 6810d 16h /or1k/tags/stable_0_2_0/
1625 First Import of uClinux for RC20x board jcastillo 6810d 16h /or1k/tags/stable_0_2_0/
1624 First Import of uClinux for RC20x board jcastillo 6810d 17h /or1k/tags/stable_0_2_0/
1623 First Import of uClinux for RC20x board jcastillo 6810d 17h /or1k/tags/stable_0_2_0/
1622 First Import of uClinux for RC20x board jcastillo 6810d 17h /or1k/tags/stable_0_2_0/
1621 First Impot jcastillo 6810d 18h /or1k/tags/stable_0_2_0/
1620 Added SMC91C111 LAN Chip Interruption to work with uClinux jcastillo 6815d 14h /or1k/tags/stable_0_2_0/
1619 Fixed types in function declaration jcastillo 6815d 19h /or1k/tags/stable_0_2_0/
1618 Import of or32 sepcific part of binutils port updated by Balint and Nog phoenix 6816d 01h /or1k/tags/stable_0_2_0/
1617 *** empty log message *** phoenix 6816d 01h /or1k/tags/stable_0_2_0/
1616 Import of or32 sepcific part of binutils port updated by Balint and Nog phoenix 6816d 01h /or1k/tags/stable_0_2_0/
1615 *** empty log message *** phoenix 6816d 02h /or1k/tags/stable_0_2_0/
1614 CI should not be set in dMMU translation tables or one gets different behaviour with dMMU on or off in case data cache is enabled. care should be taken for addresses higher than 0x7fff_ffff where the situation is just reversed. (since or1200 does not cache upper half of address space if there is no dMMU) phoenix 6826d 02h /or1k/tags/stable_0_2_0/
1613 change default phoenix 6831d 11h /or1k/tags/stable_0_2_0/
1612 major optimizations for or32 target phoenix 6831d 12h /or1k/tags/stable_0_2_0/
1610 Update ChangeLog nogj 6834d 13h /or1k/tags/stable_0_2_0/
1609 0.2.0-rc2 release nogj 6834d 14h /or1k/tags/stable_0_2_0/
1608 Avoid scheduleing too many jobs, potentially underflowing the scheduler stack nogj 6835d 08h /or1k/tags/stable_0_2_0/
1607 Don't drop cycles from the scheduler nogj 6835d 08h /or1k/tags/stable_0_2_0/
1606 fix uninitialized reads phoenix 6835d 13h /or1k/tags/stable_0_2_0/
1605 Execute l.ff1 instruction nogj 6842d 08h /or1k/tags/stable_0_2_0/
1604 Fix dumphex/dumpverilog to not do unaligned memory access nogj 6842d 08h /or1k/tags/stable_0_2_0/

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