OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [stable_0_2_0/] [or1ksim/] - Rev 1765

Rev

Filtering Options

Clear current filter

Rev Log message Author Age Path
1765 root 5561d 14h /or1k/tags/stable_0_2_0/or1ksim/
1647 This commit was manufactured by cvs2svn to create tag 'stable_0_2_0'. 6708d 17h /or1k/tags/stable_0_2_0/or1ksim/
1646 This commit was manufactured by cvs2svn to create branch 'stable_0_2_x'. 6708d 17h /or1k/tags/stable_0_2_0/or1ksim/
1645 Or1ksim release 0.2.0 nogj 6708d 17h /or1k/tags/stable_0_2_0/or1ksim/
1644 Update ChangeLog nogj 6708d 17h /or1k/tags/stable_0_2_0/or1ksim/
1643 Fix segmentation fault if setting a breakpoint on a non-existing label nogj 6708d 17h /or1k/tags/stable_0_2_0/or1ksim/
1642 Release 0.2.0-rc3 nogj 6719d 19h /or1k/tags/stable_0_2_0/or1ksim/
1641 Update ChangeLog nogj 6719d 19h /or1k/tags/stable_0_2_0/or1ksim/
1640 Upgrade cvs2cl.pl to version 2.59 nogj 6719d 19h /or1k/tags/stable_0_2_0/or1ksim/
1637 *** empty log message *** rezso 6723d 03h /or1k/tags/stable_0_2_0/or1ksim/
1619 Fixed types in function declaration jcastillo 6743d 05h /or1k/tags/stable_0_2_0/or1ksim/
1614 CI should not be set in dMMU translation tables or one gets different behaviour with dMMU on or off in case data cache is enabled. care should be taken for addresses higher than 0x7fff_ffff where the situation is just reversed. (since or1200 does not cache upper half of address space if there is no dMMU) phoenix 6753d 12h /or1k/tags/stable_0_2_0/or1ksim/
1610 Update ChangeLog nogj 6761d 23h /or1k/tags/stable_0_2_0/or1ksim/
1609 0.2.0-rc2 release nogj 6762d 00h /or1k/tags/stable_0_2_0/or1ksim/
1608 Avoid scheduleing too many jobs, potentially underflowing the scheduler stack nogj 6762d 18h /or1k/tags/stable_0_2_0/or1ksim/
1607 Don't drop cycles from the scheduler nogj 6762d 18h /or1k/tags/stable_0_2_0/or1ksim/
1606 fix uninitialized reads phoenix 6762d 23h /or1k/tags/stable_0_2_0/or1ksim/
1605 Execute l.ff1 instruction nogj 6769d 18h /or1k/tags/stable_0_2_0/or1ksim/
1604 Fix dumphex/dumpverilog to not do unaligned memory access nogj 6769d 18h /or1k/tags/stable_0_2_0/or1ksim/
1598 Handle ethernet addresses as an address and not as an int nogj 6781d 20h /or1k/tags/stable_0_2_0/or1ksim/
1597 Fix parsing the destination register nogj 6781d 20h /or1k/tags/stable_0_2_0/or1ksim/
1596 Fix handling of eof in the sim cli nogj 6781d 20h /or1k/tags/stable_0_2_0/or1ksim/
1595 Add default immu/dmmu page size nogj 6781d 20h /or1k/tags/stable_0_2_0/or1ksim/
1594 Fix the case of is_power2(0) nogj 6781d 20h /or1k/tags/stable_0_2_0/or1ksim/
1593 Don't kill sim on second ctrl+c if the cli prompt has already been shown nogj 6781d 20h /or1k/tags/stable_0_2_0/or1ksim/
1590 Added l.fl1 lampret 6784d 18h /or1k/tags/stable_0_2_0/or1ksim/
1589 Make -d channel be equivalent to -d +channel nogj 6788d 05h /or1k/tags/stable_0_2_0/or1ksim/
1588 Correct INT_MAX->INT32_MAX nogj 6788d 06h /or1k/tags/stable_0_2_0/or1ksim/
1586 Charles Qi
Fix memory handling on big endian machines		 nogj 6792d 22h /or1k/tags/stable_0_2_0/or1ksim/
1585 added missing exception, fixes segfault with trap exception phoenix 6798d 14h /or1k/tags/stable_0_2_0/or1ksim/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.