OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [stable_0_2_0/] [or1ksim/] [peripheral/] - Rev 445

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
445 Reading GPIO input reg now also returns values on output bits erez 8248d 17h /or1k/tags/stable_0_2_0/or1ksim/peripheral/
444 Added GPIO simulation erez 8249d 02h /or1k/tags/stable_0_2_0/or1ksim/peripheral/
439 Added "fake" JTAG proxy log to vapi log file erez 8249d 10h /or1k/tags/stable_0_2_0/or1ksim/peripheral/
424 memory configuration file joined into .cfg file; *mem.cfg are obsolete; read-only and write-only memory is supported; memory logging is not yet supported; update of testbench - only cache test fails, since it writes to RO memory markom 8250d 14h /or1k/tags/stable_0_2_0/or1ksim/peripheral/
423 changed break behaviour and interrupt pending; interrupt line chabnged to 15; sync bug in mode switch markom 8251d 09h /or1k/tags/stable_0_2_0/or1ksim/peripheral/
418 Renamed ethernet's RX_BD_NUM to TX_BD_NUM (following change in original files) erez 8252d 03h /or1k/tags/stable_0_2_0/or1ksim/peripheral/
411 acv uart testsuite now works (without modem test) markom 8254d 14h /or1k/tags/stable_0_2_0/or1ksim/peripheral/
409 some minor changes to or1ksim; Testbench except.s modified. Interrupt test almost finished for uart ACV. markom 8255d 14h /or1k/tags/stable_0_2_0/or1ksim/peripheral/
408 Fixed errant rx_bd_num erez 8256d 10h /or1k/tags/stable_0_2_0/or1ksim/peripheral/
406 Renamed ethernet's RX_BD_ADR to RX_BD_NUM erez 8256d 13h /or1k/tags/stable_0_2_0/or1ksim/peripheral/
398 added register field defines ivang 8263d 10h /or1k/tags/stable_0_2_0/or1ksim/peripheral/
385 check testbench now modified to work with new report output markom 8264d 10h /or1k/tags/stable_0_2_0/or1ksim/peripheral/
371 steps toward joining or32.c and opcode/or32.h of or1ksim and gdb; decode.c moved to or32.c markom 8265d 14h /or1k/tags/stable_0_2_0/or1ksim/peripheral/
361 set config command added; config struct has been divided into two structs - config and runtime; -f option allows multiple config scripts markom 8270d 16h /or1k/tags/stable_0_2_0/or1ksim/peripheral/
355 uart VAPI model improved; changes to MC and eth. markom 8271d 13h /or1k/tags/stable_0_2_0/or1ksim/peripheral/
347 Added CRC32 calculation to Ethernet erez 8277d 09h /or1k/tags/stable_0_2_0/or1ksim/peripheral/
346 Improved Ethernet simulation erez 8277d 10h /or1k/tags/stable_0_2_0/or1ksim/peripheral/
344 added acv test for uart; sim debug now has verbose levels; lot of bugs fixed in uart model markom 8277d 13h /or1k/tags/stable_0_2_0/or1ksim/peripheral/
341 added VAPI for uart; uart 16550 support, some bugs fixed markom 8278d 13h /or1k/tags/stable_0_2_0/or1ksim/peripheral/
336 VAPI works markom 8279d 09h /or1k/tags/stable_0_2_0/or1ksim/peripheral/
332 removed fixed irq numbering from pic.h; tick timer section added markom 8279d 16h /or1k/tags/stable_0_2_0/or1ksim/peripheral/
324 added initial ethernet RX simulation (very simple for now) erez 8281d 02h /or1k/tags/stable_0_2_0/or1ksim/peripheral/
307 ignore reset if ethernet is disabled markom 8283d 12h /or1k/tags/stable_0_2_0/or1ksim/peripheral/
293 added draft VAPI files; added verbose option to sim section markom 8284d 17h /or1k/tags/stable_0_2_0/or1ksim/peripheral/
261 modified memory accesses; added cfg script; added pic test basic entry of vga; some extensions to mc markom 8289d 14h /or1k/tags/stable_0_2_0/or1ksim/peripheral/
257 Added initial Ethernet simulation (only TX as yet) erez 8291d 07h /or1k/tags/stable_0_2_0/or1ksim/peripheral/
256 fixed masked_increase() in dma.c erez 8291d 07h /or1k/tags/stable_0_2_0/or1ksim/peripheral/
253 Made macros slightly more robust erez 8291d 10h /or1k/tags/stable_0_2_0/or1ksim/peripheral/
252 Fixed typo erez 8291d 11h /or1k/tags/stable_0_2_0/or1ksim/peripheral/
241 "make install" now works markom 8297d 15h /or1k/tags/stable_0_2_0/or1ksim/peripheral/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.