OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [stable_0_2_0_rc1/] - Rev 1544

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
1544 Print the exit code in decimal, like with the complex execution nogj 6942d 00h /or1k/tags/stable_0_2_0_rc1/
1543 Try to find a symbolic name of the location where we crashed nogj 6942d 00h /or1k/tags/stable_0_2_0_rc1/
1542 Print stackdump to stderr instead of stdout nogj 6942d 00h /or1k/tags/stable_0_2_0_rc1/
1541 Print the scheduler jobs when the sched_jobs debug channel has been specified nogj 6942d 00h /or1k/tags/stable_0_2_0_rc1/
1540 * Breakup the tick_job function into smaller ones.
* Fix lots of conner cases.
* Add tests for the tick timer.		 nogj 6942d 00h /or1k/tags/stable_0_2_0_rc1/
1539 Speed up the dmmu nogj 6942d 14h /or1k/tags/stable_0_2_0_rc1/
1538 Speed up the immu nogj 6942d 14h /or1k/tags/stable_0_2_0_rc1/
1537 Remove old spr logging code. Use `-d +spr' to get spr access logged to stderr nogj 6942d 14h /or1k/tags/stable_0_2_0_rc1/
1536 Add README.or32 robertmh 6943d 21h /or1k/tags/stable_0_2_0_rc1/
1534 Import of Glibc robertmh 6943d 21h /or1k/tags/stable_0_2_0_rc1/
1533 Add missing newline at EOF robertmh 6944d 20h /or1k/tags/stable_0_2_0_rc1/
1532 Add pretty spr dumping code nogj 6946d 00h /or1k/tags/stable_0_2_0_rc1/
1531 Remove non-trigerable out-of-range checks nogj 6946d 00h /or1k/tags/stable_0_2_0_rc1/
1530 Move the checking of the debug channel into the TRACE() macro nogj 6946d 00h /or1k/tags/stable_0_2_0_rc1/
1529 * The effective address as written to the I/DCBPR registers needs to be translated by the respective mmu.
* Don't treat any values as special in the handling of DCPBR, DCBFR, DCBIR, ICBPR and ICBIR.		 nogj 6947d 02h /or1k/tags/stable_0_2_0_rc1/
1528 s/HAS_ISBLANK/HAVE_ISBLANK/ fix compileing on windows/cygwin. Reported by Kuoping Hsu and Girish Venkatar nogj 6947d 08h /or1k/tags/stable_0_2_0_rc1/
1527 Fix the execution log when an mtspr instruction causes an itlb miss nogj 6947d 08h /or1k/tags/stable_0_2_0_rc1/
1526 Fix a very outdated comment nogj 6947d 08h /or1k/tags/stable_0_2_0_rc1/
1525 Rename ADDR_PAGE to IADDR_PAGE nogj 6947d 08h /or1k/tags/stable_0_2_0_rc1/
1524 Check OR32_IF_DELAY instead of it_jump || it_branch nogj 6947d 08h /or1k/tags/stable_0_2_0_rc1/
1523 Bring config files up-to-date with recent changes nogj 6947d 08h /or1k/tags/stable_0_2_0_rc1/
1522 Add the cycles debug channel to print the value of the cycle counter before each line nogj 6947d 08h /or1k/tags/stable_0_2_0_rc1/
1521 Add {TRACE,ERR,FIXME,WARN}_ON macros to get the state of the given debug channel nogj 6947d 08h /or1k/tags/stable_0_2_0_rc1/
1520 Remove unused code nogj 6947d 08h /or1k/tags/stable_0_2_0_rc1/
1519 Add a usefull trace to the mc nogj 6947d 08h /or1k/tags/stable_0_2_0_rc1/
1518 Print a '\n' at the end of the trace nogj 6947d 08h /or1k/tags/stable_0_2_0_rc1/
1517 Use uint8_t instead of char nogj 6947d 08h /or1k/tags/stable_0_2_0_rc1/
1516 Make non-writeable memory writeable by the debug core nogj 6947d 08h /or1k/tags/stable_0_2_0_rc1/
1515 Use the new debug channel code instead of a compile time macro nogj 6947d 08h /or1k/tags/stable_0_2_0_rc1/
1514 Fix compileation with --enable-execution=simple nogj 6947d 08h /or1k/tags/stable_0_2_0_rc1/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.