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[/] [or1k/] [tags/] [stable_0_2_0_rc1/] - Rev 805

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Rev Log message Author Age Path
805 kbd, fb, vga devices now uses scheduler markom 8116d 11h /or1k/tags/stable_0_2_0_rc1/
804 memory regions can now overlap with MC -- not according to MC spec markom 8117d 05h /or1k/tags/stable_0_2_0_rc1/
803 Free irq handler fixed. simons 8119d 22h /or1k/tags/stable_0_2_0_rc1/
802 Cache and tick timer tests fixed. simons 8121d 09h /or1k/tags/stable_0_2_0_rc1/
801 l.muli instruction added markom 8123d 05h /or1k/tags/stable_0_2_0_rc1/
800 Bug fixed. simons 8124d 03h /or1k/tags/stable_0_2_0_rc1/
799 Wrapping around 512k boundary to simulate real hw. simons 8127d 20h /or1k/tags/stable_0_2_0_rc1/
798 Hardware scroll added. This possible due to the fact that crt is wrapping around 512k boundary. simons 8127d 20h /or1k/tags/stable_0_2_0_rc1/
797 Changed hardcoded address for fake MC to use a define. lampret 8127d 21h /or1k/tags/stable_0_2_0_rc1/
796 Removed unused ports wb_clki and wb_rst_i lampret 8127d 21h /or1k/tags/stable_0_2_0_rc1/
795 Added a directive to ignore signed division variables that are only used in simulation. lampret 8128d 02h /or1k/tags/stable_0_2_0_rc1/
794 Added again just recently removed full_case directive lampret 8128d 02h /or1k/tags/stable_0_2_0_rc1/
793 Added synthesis off/on for timescale.v included file. lampret 8128d 02h /or1k/tags/stable_0_2_0_rc1/
792 Fixed port names that changed. lampret 8128d 02h /or1k/tags/stable_0_2_0_rc1/
791 Fixed some ports in instnatiations that were removed from the modules lampret 8128d 02h /or1k/tags/stable_0_2_0_rc1/
790 Changed comment about synopsys to _synopsys_ because synthesis was complaining about unknown directives lampret 8128d 02h /or1k/tags/stable_0_2_0_rc1/
789 Added response from memory controller (addr 0x60000000) lampret 8128d 03h /or1k/tags/stable_0_2_0_rc1/
788 Some of the warnings fixed. lampret 8128d 03h /or1k/tags/stable_0_2_0_rc1/
787 Added romfs.tgz lampret 8128d 21h /or1k/tags/stable_0_2_0_rc1/
786 Moved UCF constraint file to the backend directory. lampret 8128d 21h /or1k/tags/stable_0_2_0_rc1/
785 Added XSV specific documentation. lampret 8128d 22h /or1k/tags/stable_0_2_0_rc1/
784 Added soem missing files. lampret 8128d 22h /or1k/tags/stable_0_2_0_rc1/
783 Added sim directory and sub files/dirs. lampret 8128d 22h /or1k/tags/stable_0_2_0_rc1/
782 Added the old SW directory. It needs to be updated for the new ORP environment and test cases moved to sw directory. lampret 8128d 22h /or1k/tags/stable_0_2_0_rc1/
781 Added design compiler scripts. However these are not ready for use yet .... They need to be updated for the ORP sources and ORP sources need to be updated as well. lampret 8128d 22h /or1k/tags/stable_0_2_0_rc1/
780 Added libraries. lampret 8128d 22h /or1k/tags/stable_0_2_0_rc1/
779 Added bench directory lampret 8128d 22h /or1k/tags/stable_0_2_0_rc1/
778 Added second type of Virtual Silicon two-port SRAM (for register file). Changed defines for VS STP RAMs. lampret 8128d 23h /or1k/tags/stable_0_2_0_rc1/
777 Changed define name from OR1200_MEM2REG_FAST to OR1200_IMPL_MEM2REG2 lampret 8128d 23h /or1k/tags/stable_0_2_0_rc1/
776 Updated defines. lampret 8128d 23h /or1k/tags/stable_0_2_0_rc1/

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