OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [stable_0_2_0_rc1/] - Rev 92

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
92 Tick timer. lampret 8565d 23h /or1k/tags/stable_0_2_0_rc1/
91 Tick timer facility. lampret 8565d 23h /or1k/tags/stable_0_2_0_rc1/
90 Added tick timer. lampret 8566d 00h /or1k/tags/stable_0_2_0_rc1/
89 Minor changes. lampret 8566d 21h /or1k/tags/stable_0_2_0_rc1/
88 Update. lampret 8567d 07h /or1k/tags/stable_0_2_0_rc1/
87 Files required for creation of html files. lampret 8567d 08h /or1k/tags/stable_0_2_0_rc1/
86 Added dh command. lampret 8567d 08h /or1k/tags/stable_0_2_0_rc1/
85 Added dumphex. lampret 8567d 08h /or1k/tags/stable_0_2_0_rc1/
84 Update. lampret 8567d 08h /or1k/tags/stable_0_2_0_rc1/
83 Updates. lampret 8567d 08h /or1k/tags/stable_0_2_0_rc1/
82 Changed pctemp to pcnext. lampret 8567d 08h /or1k/tags/stable_0_2_0_rc1/
80 First import. lampret 8595d 03h /or1k/tags/stable_0_2_0_rc1/
79 Data and instruction cache simulation added. lampret 8597d 00h /or1k/tags/stable_0_2_0_rc1/
78 (i/d)tlb_status lampret 8720d 14h /or1k/tags/stable_0_2_0_rc1/
77 Regular update. lampret 8720d 14h /or1k/tags/stable_0_2_0_rc1/
76 regular update lampret 8720d 14h /or1k/tags/stable_0_2_0_rc1/
75 simgetstr added. eval_mem32 replaced with evalsim_mem32. lampret 8720d 14h /or1k/tags/stable_0_2_0_rc1/
74 Same as DMMU. lampret 8727d 13h /or1k/tags/stable_0_2_0_rc1/
73 Fixed all bugs. Now more or less works. IMMU still has some problems (exception start). lampret 8727d 13h /or1k/tags/stable_0_2_0_rc1/
72 Added 'how to build GNU tools' lampret 8732d 14h /or1k/tags/stable_0_2_0_rc1/
71 Clean two typos. lampret 8737d 16h /or1k/tags/stable_0_2_0_rc1/
70 Basic setjmp/longjmp are ready. lampret 8737d 16h /or1k/tags/stable_0_2_0_rc1/
69 Sim debug. lampret 8739d 13h /or1k/tags/stable_0_2_0_rc1/
68 Added hook for l.sys 204. Changed SPR of flag (no more CCR) lampret 8739d 14h /or1k/tags/stable_0_2_0_rc1/
67 Added simulator "application load". lampret 8739d 14h /or1k/tags/stable_0_2_0_rc1/
66 Added another set of eval_ functions that should be used directly by simulator.
evalsim_ and setsim_ don't go through MMU transaltion mechanism.		 lampret 8739d 14h /or1k/tags/stable_0_2_0_rc1/
65 Added DMMU stats. lampret 8739d 14h /or1k/tags/stable_0_2_0_rc1/
64 SPR bit definition moved to spr_defs.h. lampret 8739d 14h /or1k/tags/stable_0_2_0_rc1/
63 Fixed a bug in getsprbits/setsprbits functions (now mask can have arbitry
alignment of bits).		 lampret 8739d 14h /or1k/tags/stable_0_2_0_rc1/
62 OR1K DMMU model. lampret 8739d 14h /or1k/tags/stable_0_2_0_rc1/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.