OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [stable_0_2_0_rc1/] [gen_or1k_isa/] [sources/] [opcode/] - Rev 1341

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
1341 Mark wich operand is the destination operand in the architechture definition nogj 7105d 01h /or1k/tags/stable_0_2_0_rc1/gen_or1k_isa/sources/opcode/
1338 l.ff1 instruction added andreje 7120d 23h /or1k/tags/stable_0_2_0_rc1/gen_or1k_isa/sources/opcode/
1309 removed includes phoenix 7293d 18h /or1k/tags/stable_0_2_0_rc1/gen_or1k_isa/sources/opcode/
1308 Gyorgy Jeney: extensive cleanup phoenix 7296d 16h /or1k/tags/stable_0_2_0_rc1/gen_or1k_isa/sources/opcode/
1295 Updated instruction set descriptions. Changed FP instructions encoding. lampret 7318d 16h /or1k/tags/stable_0_2_0_rc1/gen_or1k_isa/sources/opcode/
1286 Changed desciption of the l.cust5 insns lampret 7367d 19h /or1k/tags/stable_0_2_0_rc1/gen_or1k_isa/sources/opcode/
1285 Changed desciption of the l.cust5 insns lampret 7367d 19h /or1k/tags/stable_0_2_0_rc1/gen_or1k_isa/sources/opcode/
1169 Added support for l.addc instruction. csanchez 7680d 19h /or1k/tags/stable_0_2_0_rc1/gen_or1k_isa/sources/opcode/
1114 Added cvs log keywords lampret 7835d 11h /or1k/tags/stable_0_2_0_rc1/gen_or1k_isa/sources/opcode/
1034 Fixed encoding for l.div/l.divu. lampret 7977d 12h /or1k/tags/stable_0_2_0_rc1/gen_or1k_isa/sources/opcode/
879 Initial version of OpenRISC Custom Unit Compiler added markom 8042d 22h /or1k/tags/stable_0_2_0_rc1/gen_or1k_isa/sources/opcode/
801 l.muli instruction added markom 8135d 02h /or1k/tags/stable_0_2_0_rc1/gen_or1k_isa/sources/opcode/
722 floating point registers are obsolete; GPRs should be used instead markom 8163d 01h /or1k/tags/stable_0_2_0_rc1/gen_or1k_isa/sources/opcode/
720 single floating point support added markom 8163d 05h /or1k/tags/stable_0_2_0_rc1/gen_or1k_isa/sources/opcode/
717 some minor improvements markom 8163d 07h /or1k/tags/stable_0_2_0_rc1/gen_or1k_isa/sources/opcode/
714 do_stats introduced for faster no-stats execution markom 8165d 03h /or1k/tags/stable_0_2_0_rc1/gen_or1k_isa/sources/opcode/
709 eval_operands is now being generated markom 8168d 08h /or1k/tags/stable_0_2_0_rc1/gen_or1k_isa/sources/opcode/
706 insn_decode execution part replaced by generated function decode_execute; use --enable-simple to use runtime decoding markom 8169d 01h /or1k/tags/stable_0_2_0_rc1/gen_or1k_isa/sources/opcode/
703 small optimizations to dissasemble markom 8170d 05h /or1k/tags/stable_0_2_0_rc1/gen_or1k_isa/sources/opcode/
676 update of shared files markom 8182d 01h /or1k/tags/stable_0_2_0_rc1/gen_or1k_isa/sources/opcode/
671 wrong version was restored markom 8182d 06h /or1k/tags/stable_0_2_0_rc1/gen_or1k_isa/sources/opcode/
662 GNU binutils merge. ivang 8186d 03h /or1k/tags/stable_0_2_0_rc1/gen_or1k_isa/sources/opcode/
627 or32 restored markom 8199d 06h /or1k/tags/stable_0_2_0_rc1/gen_or1k_isa/sources/opcode/
623 update based on recent changes; arithmetic instructions does not modify carry yet markom 8200d 00h /or1k/tags/stable_0_2_0_rc1/gen_or1k_isa/sources/opcode/
615 cmov and extxx instructions; add, addi, and, andi now set flag markom 8203d 00h /or1k/tags/stable_0_2_0_rc1/gen_or1k_isa/sources/opcode/
508 nop instruction now has immediate markom 8225d 02h /or1k/tags/stable_0_2_0_rc1/gen_or1k_isa/sources/opcode/
497 Fixed encoding of the following insns: l.mac,l.msb,l.maci,l.mtspr,l.mfspr lampret 8237d 14h /or1k/tags/stable_0_2_0_rc1/gen_or1k_isa/sources/opcode/
374 *** empty log message *** simons 8262d 22h /or1k/tags/stable_0_2_0_rc1/gen_or1k_isa/sources/opcode/
371 steps toward joining or32.c and opcode/or32.h of or1ksim and gdb; decode.c moved to or32.c markom 8263d 05h /or1k/tags/stable_0_2_0_rc1/gen_or1k_isa/sources/opcode/
355 uart VAPI model improved; changes to MC and eth. markom 8269d 03h /or1k/tags/stable_0_2_0_rc1/gen_or1k_isa/sources/opcode/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.