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[/] [or1k/] [tags/] [stable_0_2_0_rc2/] [or1ksim/] [cache/] - Rev 1765

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1765 root 5587d 21h /or1k/tags/stable_0_2_0_rc2/or1ksim/cache/
1611 This commit was manufactured by cvs2svn to create tag 'stable_0_2_0_rc2'. 6788d 06h /or1k/tags/stable_0_2_0_rc2/or1ksim/cache/
1576 configure updates phoenix 6846d 21h /or1k/tags/stable_0_2_0_rc2/or1ksim/cache/
1557 Fix most warnings issued by gcc4 nogj 6870d 11h /or1k/tags/stable_0_2_0_rc2/or1ksim/cache/
1555 * Moved log2_int() from cuc/cuc.c as it is usefull for other things aswell.
* Changed code to use log2_int() instead of log2(), which is also a builtin
library function (fixes compile on gcc4).
* Moved is_power2() from sim-config.c to misc.c.		 nogj 6870d 11h /or1k/tags/stable_0_2_0_rc2/or1ksim/cache/
1506 * Remove very slow {set,test}sprbit{,s} functions.
* Remove uses of getsprbits in time critical functions.		 nogj 6937d 08h /or1k/tags/stable_0_2_0_rc2/or1ksim/cache/
1486 * Seporate out the code used for handling the memory peripheral to peripheral/memory.c
* Mostly decouple the memory controller from the internals of the memory handling.
* Rewrite memory handling to be more linear and thus much faster.
* Issue a bus error on read/write with invalid granularity.		 nogj 6980d 09h /or1k/tags/stable_0_2_0_rc2/or1ksim/cache/
1432 Collect most of the cpu state variables in a structure (cpu_state) nogj 7028d 04h /or1k/tags/stable_0_2_0_rc2/or1ksim/cache/
1406 Fix the declaration of `sec' in reg_ic_sec nogj 7028d 04h /or1k/tags/stable_0_2_0_rc2/or1ksim/cache/
1404 Move the function of ic_clock() to mtspr() and remove it nogj 7028d 04h /or1k/tags/stable_0_2_0_rc2/or1ksim/cache/
1402 Do what dc_clock() did in mtspr() and remove it nogj 7028d 04h /or1k/tags/stable_0_2_0_rc2/or1ksim/cache/
1386 Rework exception handling nogj 7034d 07h /or1k/tags/stable_0_2_0_rc2/or1ksim/cache/
1382 Nir Mor:
Implemented DCCFGR, ICCFGR, DMMUCFGR and IMMUCFGR spr registers.		 nogj 7043d 08h /or1k/tags/stable_0_2_0_rc2/or1ksim/cache/
1376 aclocal && autoconf && automake phoenix 7062d 08h /or1k/tags/stable_0_2_0_rc2/or1ksim/cache/
1358 Modularise config file parseing. Paving the way for further modularisation. nogj 7068d 23h /or1k/tags/stable_0_2_0_rc2/or1ksim/cache/
1350 Mark a simulated cpu address as such, by introducing the new oraddr_t type nogj 7078d 02h /or1k/tags/stable_0_2_0_rc2/or1ksim/cache/
1344 * Avoid doing a store in *every* instruction executed by storeing the instruction function unit in or32_opcodes nogj 7091d 06h /or1k/tags/stable_0_2_0_rc2/or1ksim/cache/
1308 Gyorgy Jeney: extensive cleanup phoenix 7282d 21h /or1k/tags/stable_0_2_0_rc2/or1ksim/cache/
1249 Downgrading back to automake-1.4 lampret 7447d 21h /or1k/tags/stable_0_2_0_rc2/or1ksim/cache/
1117 Ignore generated files for CVS purposes sfurman 7790d 21h /or1k/tags/stable_0_2_0_rc2/or1ksim/cache/
1099 cvs bug fixed markom 7877d 08h /or1k/tags/stable_0_2_0_rc2/or1ksim/cache/
1085 Bug fixed. simons 7889d 22h /or1k/tags/stable_0_2_0_rc2/or1ksim/cache/
997 PRINTF should be used instead of printf; command redirection repaired markom 7979d 11h /or1k/tags/stable_0_2_0_rc2/or1ksim/cache/
992 A bug when cache enabled and bus error comes fixed. simons 7981d 03h /or1k/tags/stable_0_2_0_rc2/or1ksim/cache/
970 Testbench is now running on ORP architecture platform. simons 7986d 22h /or1k/tags/stable_0_2_0_rc2/or1ksim/cache/
884 code cleaning - a lot of global variables moved to runtime struct markom 8023d 09h /or1k/tags/stable_0_2_0_rc2/or1ksim/cache/
876 Beta release of ATA simulation rherveille 8030d 21h /or1k/tags/stable_0_2_0_rc2/or1ksim/cache/
638 TLBTR CI bit is now working properly. simons 8181d 23h /or1k/tags/stable_0_2_0_rc2/or1ksim/cache/
631 Real cache access is simulated now. simons 8184d 22h /or1k/tags/stable_0_2_0_rc2/or1ksim/cache/
626 store buffer added markom 8185d 11h /or1k/tags/stable_0_2_0_rc2/or1ksim/cache/

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