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[/] [or1k/] [tags/] [stable_0_2_0_rc2/] [or1ksim/] [cpu/] [or1k/] - Rev 1510

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1510 Create a seporate debug channel to dump exceptions to nogj 6973d 07h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or1k/
1509 Remove 08 prefix from PRIdREG nogj 6973d 07h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or1k/
1508 Remove m{f,t}spr calls where we can access the spr directly nogj 6973d 07h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or1k/
1506 * Remove very slow {set,test}sprbit{,s} functions.
* Remove uses of getsprbits in time critical functions.
nogj 6973d 07h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or1k/
1486 * Seporate out the code used for handling the memory peripheral to peripheral/memory.c
* Mostly decouple the memory controller from the internals of the memory handling.
* Rewrite memory handling to be more linear and thus much faster.
* Issue a bus error on read/write with invalid granularity.
nogj 7016d 07h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or1k/
1481 Remove the useless cross reference stuff: it was a bad idea to begin with nogj 7036d 23h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or1k/
1473 Add warning that except_handle may not return nogj 7064d 02h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or1k/
1471 Rewrite the interactive mode handling to also work in the recompiler nogj 7064d 02h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or1k/
1452 Implement a dynamic recompiler to speed up the execution nogj 7064d 02h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or1k/
1446 Cosmetic fixes nogj 7064d 02h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or1k/
1444 Move the definitions needed for the simple execution model out of or32.h and into simpl32_defs.h nogj 7064d 02h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or1k/
1442 Replace some problematic calles to mfspr/mtspr with direct access to the spr nogj 7064d 02h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or1k/
1432 Collect most of the cpu state variables in a structure (cpu_state) nogj 7064d 02h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or1k/
1404 Move the function of ic_clock() to mtspr() and remove it nogj 7064d 03h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or1k/
1402 Do what dc_clock() did in mtspr() and remove it nogj 7064d 03h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or1k/
1386 Rework exception handling nogj 7070d 06h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or1k/
1382 Nir Mor:
Implemented DCCFGR, ICCFGR, DMMUCFGR and IMMUCFGR spr registers.
nogj 7079d 06h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or1k/
1376 aclocal && autoconf && automake phoenix 7098d 06h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or1k/
1354 typing fixes phoenix 7113d 03h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or1k/
1350 Mark a simulated cpu address as such, by introducing the new oraddr_t type nogj 7114d 01h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or1k/
1344 * Avoid doing a store in *every* instruction executed by storeing the instruction function unit in or32_opcodes nogj 7127d 04h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or1k/
1342 * Fix generate.c to produce a execgen.c with less warnings.
* Fix the --enable-simple configure option.
nogj 7127d 05h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or1k/
1341 Mark wich operand is the destination operand in the architechture definition nogj 7127d 05h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or1k/
1338 l.ff1 instruction added andreje 7143d 03h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or1k/
1319 cpu/sim memory accesses separation, tick, exception, nr. of operands, cycles count,... corrections. phoenix 7230d 19h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or1k/
1316 added a warning phoenix 7248d 17h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or1k/
1314 in some cases (cbasic test from orp for example) this caused problems, disable for now phoenix 7248d 17h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or1k/
1308 Gyorgy Jeney: extensive cleanup phoenix 7318d 19h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or1k/
1302 compile fix (remove const) phoenix 7336d 17h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or1k/
1263 simprintf now uses stack vargs -- same as printf markom 7434d 09h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or1k/

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