OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [stable_0_2_0_rc3/] - Rev 640

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
640 Merge profiler and mprofiler with sim. ivang 8229d 00h /or1k/tags/stable_0_2_0_rc3/
639 MMU cache inhibit bit test added. simons 8231d 15h /or1k/tags/stable_0_2_0_rc3/
638 TLBTR CI bit is now working properly. simons 8231d 15h /or1k/tags/stable_0_2_0_rc3/
637 Updated file names. lampret 8231d 16h /or1k/tags/stable_0_2_0_rc3/
636 Fixed combinational loops. lampret 8231d 16h /or1k/tags/stable_0_2_0_rc3/
635 Fixed Makefile bug. ivang 8231d 18h /or1k/tags/stable_0_2_0_rc3/
634 configure.in : fixed to build start/Makefile
start.S : l.jalr r9 -> l.jr r9

Added missing files.		 ivang 8232d 19h /or1k/tags/stable_0_2_0_rc3/
633 Bug fix in command line parser. ivang 8232d 20h /or1k/tags/stable_0_2_0_rc3/
632 profiler and mprofiler merged into sim. ivang 8233d 15h /or1k/tags/stable_0_2_0_rc3/
631 Real cache access is simulated now. simons 8234d 14h /or1k/tags/stable_0_2_0_rc3/
630 some bug fixes in store buffer analysis markom 8234d 23h /or1k/tags/stable_0_2_0_rc3/
629 typo fixed markom 8235d 03h /or1k/tags/stable_0_2_0_rc3/
627 or32 restored markom 8235d 03h /or1k/tags/stable_0_2_0_rc3/
626 store buffer added markom 8235d 03h /or1k/tags/stable_0_2_0_rc3/
625 Bus error bug fixed. Cache routines added. simons 8235d 19h /or1k/tags/stable_0_2_0_rc3/
624 Added logging of writes/read to/from SPR registers. ivang 8235d 20h /or1k/tags/stable_0_2_0_rc3/
623 update based on recent changes; arithmetic instructions does not modify carry yet markom 8235d 22h /or1k/tags/stable_0_2_0_rc3/
622 Cache test works on hardware. simons 8236d 01h /or1k/tags/stable_0_2_0_rc3/
621 Cache test works on hardware. simons 8236d 02h /or1k/tags/stable_0_2_0_rc3/
620 use ARITH_SET_FLAG to turn off set flag by arith. instructions markom 8236d 02h /or1k/tags/stable_0_2_0_rc3/
619 all test pass, after newest changes markom 8236d 02h /or1k/tags/stable_0_2_0_rc3/
618 Fixed display of new 'void' nop insns. lampret 8236d 11h /or1k/tags/stable_0_2_0_rc3/
617 Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways. lampret 8236d 11h /or1k/tags/stable_0_2_0_rc3/
616 flags test added markom 8238d 21h /or1k/tags/stable_0_2_0_rc3/
615 cmov and extxx instructions; add, addi, and, andi now set flag markom 8238d 21h /or1k/tags/stable_0_2_0_rc3/
614 Changed to support new debug if. simons 8239d 04h /or1k/tags/stable_0_2_0_rc3/
613 init: trap exception occurs always; initialization of sr not needed anymore markom 8240d 01h /or1k/tags/stable_0_2_0_rc3/
612 Tick timer period extended to meet real timing. simons 8240d 03h /or1k/tags/stable_0_2_0_rc3/
611 EEAR register is not changed by trap, sys, int, tick and range exception. simons 8241d 04h /or1k/tags/stable_0_2_0_rc3/
610 Changed default reset values for SR and ESR to match or1ksim's. Fixed flop model in or1200_dpram_32x32 when OR1200_XILINX_RAM32X1D is defined. lampret 8241d 04h /or1k/tags/stable_0_2_0_rc3/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.