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[/] [or1k/] [tags/] [stable_0_2_0_rc3/] - Rev 999

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Rev Log message Author Age Path
999 Now every ramdisk image should have init program. simons 7997d 23h /or1k/tags/stable_0_2_0_rc3/
998 added missing fout initialization markom 7998d 01h /or1k/tags/stable_0_2_0_rc3/
997 PRINTF should be used instead of printf; command redirection repaired markom 7998d 02h /or1k/tags/stable_0_2_0_rc3/
996 some minor bugs fixed markom 7999d 00h /or1k/tags/stable_0_2_0_rc3/
994 Store buffer has been tested and it works. BY default it is still disabled until uClinux confirms correct operation on FPGA board. lampret 7999d 08h /or1k/tags/stable_0_2_0_rc3/
993 Fixed IMMU bug. lampret 7999d 08h /or1k/tags/stable_0_2_0_rc3/
992 A bug when cache enabled and bus error comes fixed. simons 7999d 17h /or1k/tags/stable_0_2_0_rc3/
991 Different memory controller. simons 7999d 17h /or1k/tags/stable_0_2_0_rc3/
990 Test is now complete. simons 7999d 17h /or1k/tags/stable_0_2_0_rc3/
989 c++ is making problems so, for now, it is excluded. simons 8001d 01h /or1k/tags/stable_0_2_0_rc3/
988 ORP architecture supported. simons 8001d 16h /or1k/tags/stable_0_2_0_rc3/
987 ORP architecture supported. simons 8002d 00h /or1k/tags/stable_0_2_0_rc3/
986 outputs out of function are not registered anymore markom 8002d 00h /or1k/tags/stable_0_2_0_rc3/
985 DTLB translation doesn't work on or1ksim when IC/DC enabled. lampret 8002d 12h /or1k/tags/stable_0_2_0_rc3/
984 Disable SB until it is tested lampret 8002d 12h /or1k/tags/stable_0_2_0_rc3/
983 First checkin lampret 8002d 14h /or1k/tags/stable_0_2_0_rc3/
982 Moved to sim/bin lampret 8002d 14h /or1k/tags/stable_0_2_0_rc3/
981 First checkin. lampret 8002d 14h /or1k/tags/stable_0_2_0_rc3/
980 Removed sim.tcl that shouldn't be here. lampret 8002d 14h /or1k/tags/stable_0_2_0_rc3/
979 Removed old test case binaries. lampret 8002d 14h /or1k/tags/stable_0_2_0_rc3/
978 Added variable delay for SRAM. lampret 8002d 14h /or1k/tags/stable_0_2_0_rc3/
977 Added store buffer. lampret 8002d 14h /or1k/tags/stable_0_2_0_rc3/
976 Added store buffer lampret 8002d 14h /or1k/tags/stable_0_2_0_rc3/
975 First checkin lampret 8002d 14h /or1k/tags/stable_0_2_0_rc3/
974 Enabled what works on or1ksim and disabled other tests. lampret 8002d 16h /or1k/tags/stable_0_2_0_rc3/
973 generated cuc top scheduler builds without syntax errors; not tested yet markom 8004d 21h /or1k/tags/stable_0_2_0_rc3/
972 Interrupt suorces fixed. simons 8004d 21h /or1k/tags/stable_0_2_0_rc3/
971 Now even keyboard test passes. simons 8005d 00h /or1k/tags/stable_0_2_0_rc3/
970 Testbench is now running on ORP architecture platform. simons 8005d 12h /or1k/tags/stable_0_2_0_rc3/
969 Checking in except directory. lampret 8006d 04h /or1k/tags/stable_0_2_0_rc3/

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