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[/] [or1k/] [tags/] [stable_0_2_0_rc3/] [or1ksim/] - Rev 97

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Rev Log message Author Age Path
97 Description of all test cases (at least working one). lampret 8530d 00h /or1k/tags/stable_0_2_0_rc3/or1ksim/
94 Update. lampret 8560d 03h /or1k/tags/stable_0_2_0_rc3/or1ksim/
93 Adding uos. lampret 8560d 03h /or1k/tags/stable_0_2_0_rc3/or1ksim/
92 Tick timer. lampret 8560d 06h /or1k/tags/stable_0_2_0_rc3/or1ksim/
91 Tick timer facility. lampret 8560d 06h /or1k/tags/stable_0_2_0_rc3/or1ksim/
90 Added tick timer. lampret 8560d 08h /or1k/tags/stable_0_2_0_rc3/or1ksim/
86 Added dh command. lampret 8561d 15h /or1k/tags/stable_0_2_0_rc3/or1ksim/
85 Added dumphex. lampret 8561d 15h /or1k/tags/stable_0_2_0_rc3/or1ksim/
84 Update. lampret 8561d 15h /or1k/tags/stable_0_2_0_rc3/or1ksim/
83 Updates. lampret 8561d 15h /or1k/tags/stable_0_2_0_rc3/or1ksim/
82 Changed pctemp to pcnext. lampret 8561d 15h /or1k/tags/stable_0_2_0_rc3/or1ksim/
79 Data and instruction cache simulation added. lampret 8591d 07h /or1k/tags/stable_0_2_0_rc3/or1ksim/
78 (i/d)tlb_status lampret 8714d 21h /or1k/tags/stable_0_2_0_rc3/or1ksim/
77 Regular update. lampret 8714d 21h /or1k/tags/stable_0_2_0_rc3/or1ksim/
76 regular update lampret 8714d 21h /or1k/tags/stable_0_2_0_rc3/or1ksim/
75 simgetstr added. eval_mem32 replaced with evalsim_mem32. lampret 8714d 21h /or1k/tags/stable_0_2_0_rc3/or1ksim/
74 Same as DMMU. lampret 8721d 20h /or1k/tags/stable_0_2_0_rc3/or1ksim/
73 Fixed all bugs. Now more or less works. IMMU still has some problems (exception start). lampret 8721d 20h /or1k/tags/stable_0_2_0_rc3/or1ksim/
72 Added 'how to build GNU tools' lampret 8726d 21h /or1k/tags/stable_0_2_0_rc3/or1ksim/
69 Sim debug. lampret 8733d 21h /or1k/tags/stable_0_2_0_rc3/or1ksim/
68 Added hook for l.sys 204. Changed SPR of flag (no more CCR) lampret 8733d 21h /or1k/tags/stable_0_2_0_rc3/or1ksim/
67 Added simulator "application load". lampret 8733d 21h /or1k/tags/stable_0_2_0_rc3/or1ksim/
66 Added another set of eval_ functions that should be used directly by simulator.
evalsim_ and setsim_ don't go through MMU transaltion mechanism.		 lampret 8733d 21h /or1k/tags/stable_0_2_0_rc3/or1ksim/
65 Added DMMU stats. lampret 8733d 21h /or1k/tags/stable_0_2_0_rc3/or1ksim/
64 SPR bit definition moved to spr_defs.h. lampret 8733d 21h /or1k/tags/stable_0_2_0_rc3/or1ksim/
63 Fixed a bug in getsprbits/setsprbits functions (now mask can have arbitry
alignment of bits).		 lampret 8733d 21h /or1k/tags/stable_0_2_0_rc3/or1ksim/
62 OR1K DMMU model. lampret 8733d 21h /or1k/tags/stable_0_2_0_rc3/or1ksim/
60 Memory model changed. lampret 8769d 00h /or1k/tags/stable_0_2_0_rc3/or1ksim/
55 Added 'dv' command for dumping memory as verilog model. lampret 8784d 21h /or1k/tags/stable_0_2_0_rc3/or1ksim/
54 Regular maintenance. lampret 8784d 21h /or1k/tags/stable_0_2_0_rc3/or1ksim/

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