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[/] [or1k/] [tags/] [stable_0_2_0_rc3/] [or1ksim/] [mmu/] - Rev 1532

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Rev Log message Author Age Path
1532 Add pretty spr dumping code nogj 6946d 12h /or1k/tags/stable_0_2_0_rc3/or1ksim/mmu/
1508 Remove m{f,t}spr calls where we can access the spr directly nogj 6947d 20h /or1k/tags/stable_0_2_0_rc3/or1ksim/mmu/
1506 * Remove very slow {set,test}sprbit{,s} functions.
* Remove uses of getsprbits in time critical functions.		 nogj 6947d 20h /or1k/tags/stable_0_2_0_rc3/or1ksim/mmu/
1446 Cosmetic fixes nogj 7038d 16h /or1k/tags/stable_0_2_0_rc3/or1ksim/mmu/
1432 Collect most of the cpu state variables in a structure (cpu_state) nogj 7038d 16h /or1k/tags/stable_0_2_0_rc3/or1ksim/mmu/
1418 Rearange some code such that it is not assumed that except_handle returns nogj 7038d 16h /or1k/tags/stable_0_2_0_rc3/or1ksim/mmu/
1416 Make the immu use the new debug functions nogj 7038d 16h /or1k/tags/stable_0_2_0_rc3/or1ksim/mmu/
1414 Rearange code in the dmmu such that it is not assumed that except_handle returns nogj 7038d 16h /or1k/tags/stable_0_2_0_rc3/or1ksim/mmu/
1412 Make the dmmu use the new debug functions nogj 7038d 16h /or1k/tags/stable_0_2_0_rc3/or1ksim/mmu/
1382 Nir Mor:
Implemented DCCFGR, ICCFGR, DMMUCFGR and IMMUCFGR spr registers.		 nogj 7053d 20h /or1k/tags/stable_0_2_0_rc3/or1ksim/mmu/
1376 aclocal && autoconf && automake phoenix 7072d 20h /or1k/tags/stable_0_2_0_rc3/or1ksim/mmu/
1358 Modularise config file parseing. Paving the way for further modularisation. nogj 7079d 11h /or1k/tags/stable_0_2_0_rc3/or1ksim/mmu/
1350 Mark a simulated cpu address as such, by introducing the new oraddr_t type nogj 7088d 14h /or1k/tags/stable_0_2_0_rc3/or1ksim/mmu/
1344 * Avoid doing a store in *every* instruction executed by storeing the instruction function unit in or32_opcodes nogj 7101d 18h /or1k/tags/stable_0_2_0_rc3/or1ksim/mmu/
1308 Gyorgy Jeney: extensive cleanup phoenix 7293d 09h /or1k/tags/stable_0_2_0_rc3/or1ksim/mmu/
1249 Downgrading back to automake-1.4 lampret 7458d 09h /or1k/tags/stable_0_2_0_rc3/or1ksim/mmu/
1240 additional functions to bypass cache and mmu needed for peripheral devices phoenix 7465d 04h /or1k/tags/stable_0_2_0_rc3/or1ksim/mmu/
1174 fix for immu exceptions that never should have happened phoenix 7669d 08h /or1k/tags/stable_0_2_0_rc3/or1ksim/mmu/
1117 Ignore generated files for CVS purposes sfurman 7801d 09h /or1k/tags/stable_0_2_0_rc3/or1ksim/mmu/
1099 cvs bug fixed markom 7887d 20h /or1k/tags/stable_0_2_0_rc3/or1ksim/mmu/
997 PRINTF should be used instead of printf; command redirection repaired markom 7989d 23h /or1k/tags/stable_0_2_0_rc3/or1ksim/mmu/
970 Testbench is now running on ORP architecture platform. simons 7997d 10h /or1k/tags/stable_0_2_0_rc3/or1ksim/mmu/
886 MMU registers reserved fields protected from writing. simons 8033d 15h /or1k/tags/stable_0_2_0_rc3/or1ksim/mmu/
884 code cleaning - a lot of global variables moved to runtime struct markom 8033d 21h /or1k/tags/stable_0_2_0_rc3/or1ksim/mmu/
876 Beta release of ATA simulation rherveille 8041d 09h /or1k/tags/stable_0_2_0_rc3/or1ksim/mmu/
713 lot of small minor improvements: code documented, cleaned; runs at about same speed when not actually logging, but exe_log is enabled; raw_stats now run only with simple execution - enable RAW_USAGE_STATS macro markom 8161d 22h /or1k/tags/stable_0_2_0_rc3/or1ksim/mmu/
638 TLBTR CI bit is now working properly. simons 8192d 11h /or1k/tags/stable_0_2_0_rc3/or1ksim/mmu/
600 No more low/high priority interrupts (PICPR removed). Added tick timer exception. simons 8205d 09h /or1k/tags/stable_0_2_0_rc3/or1ksim/mmu/
572 Some new bugs fixed. simons 8210d 11h /or1k/tags/stable_0_2_0_rc3/or1ksim/mmu/
541 lot of new parameters concerning memory delays added; bpb parameter moved from cpu to new bpb section; UPDATE YOUR .CFG FILES! markom 8216d 19h /or1k/tags/stable_0_2_0_rc3/or1ksim/mmu/

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