OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [stable_0_2_0_rc3/] [or1ksim/] [peripheral/] - Rev 257

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
257 Added initial Ethernet simulation (only TX as yet) erez 8289d 23h /or1k/tags/stable_0_2_0_rc3/or1ksim/peripheral/
256 fixed masked_increase() in dma.c erez 8289d 23h /or1k/tags/stable_0_2_0_rc3/or1ksim/peripheral/
253 Made macros slightly more robust erez 8290d 02h /or1k/tags/stable_0_2_0_rc3/or1ksim/peripheral/
252 Fixed typo erez 8290d 02h /or1k/tags/stable_0_2_0_rc3/or1ksim/peripheral/
241 "make install" now works markom 8296d 06h /or1k/tags/stable_0_2_0_rc3/or1ksim/peripheral/
239 added enviroment configuration script parser markom 8296d 07h /or1k/tags/stable_0_2_0_rc3/or1ksim/peripheral/
238 Changed function prototypes to quiet compiler warning erez 8296d 19h /or1k/tags/stable_0_2_0_rc3/or1ksim/peripheral/
235 memory areas now have a "granularity"
also switched dma to GNU coding		 erez 8296d 19h /or1k/tags/stable_0_2_0_rc3/or1ksim/peripheral/
233 Changed my email erez 8296d 22h /or1k/tags/stable_0_2_0_rc3/or1ksim/peripheral/
221 major changes to testbench; debug unit is moved to /debug; memory organization can be customized; UART from simons; overall cleanup markom 8297d 05h /or1k/tags/stable_0_2_0_rc3/or1ksim/peripheral/
212 Added DMA erez 8317d 06h /or1k/tags/stable_0_2_0_rc3/or1ksim/peripheral/
206 Several modifications to support gdb in a new exception style mode.
This new version works with gdb, and does not require the simulator
to implement a writeable PC.		 chris 8324d 08h /or1k/tags/stable_0_2_0_rc3/or1ksim/peripheral/
193 Declared RISCOP.RESET to be volatile so that -O2 optimization would
not optimize away the correct behavior by trying to be too clever.		 chris 8344d 04h /or1k/tags/stable_0_2_0_rc3/or1ksim/peripheral/
187 minor change to clear pending exception chris 8345d 09h /or1k/tags/stable_0_2_0_rc3/or1ksim/peripheral/
186 major change to UART structure chris 8345d 09h /or1k/tags/stable_0_2_0_rc3/or1ksim/peripheral/
185 major change to UART code chris 8345d 09h /or1k/tags/stable_0_2_0_rc3/or1ksim/peripheral/
167 - SPR values corrected
- testbenches now work
- lot of optimizations, use --disable-debugmod for optimal performance
- some tick timer bugs fixed		 markom 8374d 01h /or1k/tags/stable_0_2_0_rc3/or1ksim/peripheral/
148 Replace single stepping patch that got overwritten chris 8417d 12h /or1k/tags/stable_0_2_0_rc3/or1ksim/peripheral/
145 Modifications necessary for functional gdb debugging interface chris 8418d 04h /or1k/tags/stable_0_2_0_rc3/or1ksim/peripheral/
138 - on the fly insn decoding
- removed asm input file support
- removed string from execution
- speedup of loading		 markom 8421d 07h /or1k/tags/stable_0_2_0_rc3/or1ksim/peripheral/
131 Initial checkin of the Debug Unit register descriptions chris 8425d 04h /or1k/tags/stable_0_2_0_rc3/or1ksim/peripheral/
130 Initial checkin of the debug unit module chris 8425d 04h /or1k/tags/stable_0_2_0_rc3/or1ksim/peripheral/
123 Bugs fixed:
- l.rfe temporarly disables exceptions
- l.sys does PC -= 4
- breakpoints now supported at peripheria locations
- uart0.rt/.tx nonexistent file segment fault

Other modifications:
- replaced string names to instruction indexes
- execute.c executes specified (in ISA table) function
- modified ISA table - flag needed for gdb
- added or32.c, which supports or32.h
- added new instructions l.mac, l.msb, l.maci, l.macrc
and their executing functions (opcodes to be revisited)
- added header acconfig.h
- modified configuration files		 markom 8431d 02h /or1k/tags/stable_0_2_0_rc3/or1ksim/peripheral/
102 Major update to include PM, PIC, Cache Mngmnt and non-interactive mode. lampret 8456d 11h /or1k/tags/stable_0_2_0_rc3/or1ksim/peripheral/
31 16450 serial UART device. lampret 8802d 17h /or1k/tags/stable_0_2_0_rc3/or1ksim/peripheral/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.