OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [stable_0_2_0_rc3/] [or1ksim/] [tick/] - Rev 1560

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
1560 Fix bug of not reporting timer interrupts when one was pending and a write happens to the ttmr spr that is not clearing the interrupt pending flag nogj 6872d 15h /or1k/tags/stable_0_2_0_rc3/or1ksim/tick/
1559 Make the tick interrupt work when except_handle does not return nogj 6872d 15h /or1k/tags/stable_0_2_0_rc3/or1ksim/tick/
1545 move sched_next_insn from sim-cmd.c to sched.c. It is also usefull for the pic and the tick timer nogj 6934d 04h /or1k/tags/stable_0_2_0_rc3/or1ksim/tick/
1540 * Breakup the tick_job function into smaller ones.
* Fix lots of conner cases.
* Add tests for the tick timer.
nogj 6934d 04h /or1k/tags/stable_0_2_0_rc3/or1ksim/tick/
1506 * Remove very slow {set,test}sprbit{,s} functions.
* Remove uses of getsprbits in time critical functions.
nogj 6939d 12h /or1k/tags/stable_0_2_0_rc3/or1ksim/tick/
1446 Cosmetic fixes nogj 7030d 07h /or1k/tags/stable_0_2_0_rc3/or1ksim/tick/
1432 Collect most of the cpu state variables in a structure (cpu_state) nogj 7030d 07h /or1k/tags/stable_0_2_0_rc3/or1ksim/tick/
1410 Use the uorreg_t where it should be used nogj 7030d 08h /or1k/tags/stable_0_2_0_rc3/or1ksim/tick/
1408 Make the tick timer use the new debug functions nogj 7030d 08h /or1k/tags/stable_0_2_0_rc3/or1ksim/tick/
1390 * Change scheduler to count down to 0 instead of reaching a certain cycle
count.
* Change the SCHED_ADD interface to take a time out as the parameter instead of the number of cycles.
nogj 7030d 08h /or1k/tags/stable_0_2_0_rc3/or1ksim/tick/
1386 Rework exception handling nogj 7036d 11h /or1k/tags/stable_0_2_0_rc3/or1ksim/tick/
1376 aclocal && autoconf && automake phoenix 7064d 11h /or1k/tags/stable_0_2_0_rc3/or1ksim/tick/
1365 Pass a pointer as the user given argument in the schedular callback nogj 7071d 02h /or1k/tags/stable_0_2_0_rc3/or1ksim/tick/
1350 Mark a simulated cpu address as such, by introducing the new oraddr_t type nogj 7080d 06h /or1k/tags/stable_0_2_0_rc3/or1ksim/tick/
1319 cpu/sim memory accesses separation, tick, exception, nr. of operands, cycles count,... corrections. phoenix 7197d 01h /or1k/tags/stable_0_2_0_rc3/or1ksim/tick/
1249 Downgrading back to automake-1.4 lampret 7450d 00h /or1k/tags/stable_0_2_0_rc3/or1ksim/tick/
1117 Ignore generated files for CVS purposes sfurman 7793d 00h /or1k/tags/stable_0_2_0_rc3/or1ksim/tick/
997 PRINTF should be used instead of printf; command redirection repaired markom 7981d 15h /or1k/tags/stable_0_2_0_rc3/or1ksim/tick/
970 Testbench is now running on ORP architecture platform. simons 7989d 02h /or1k/tags/stable_0_2_0_rc3/or1ksim/tick/
884 code cleaning - a lot of global variables moved to runtime struct markom 8025d 13h /or1k/tags/stable_0_2_0_rc3/or1ksim/tick/
876 Beta release of ATA simulation rherveille 8033d 01h /or1k/tags/stable_0_2_0_rc3/or1ksim/tick/
802 Cache and tick timer tests fixed. simons 8121d 14h /or1k/tags/stable_0_2_0_rc3/or1ksim/tick/
728 tick timer works with scheduler markom 8150d 13h /or1k/tags/stable_0_2_0_rc3/or1ksim/tick/
611 EEAR register is not changed by trap, sys, int, tick and range exception. simons 8193d 15h /or1k/tags/stable_0_2_0_rc3/or1ksim/tick/
600 No more low/high priority interrupts (PICPR removed). Added tick timer exception. simons 8197d 01h /or1k/tags/stable_0_2_0_rc3/or1ksim/tick/
561 Tick timer is not connected to PIC. simons 8203d 06h /or1k/tags/stable_0_2_0_rc3/or1ksim/tick/
517 some performance optimizations markom 8212d 09h /or1k/tags/stable_0_2_0_rc3/or1ksim/tick/
500 Added .cvsignore files for annoying generated files erez 8214d 13h /or1k/tags/stable_0_2_0_rc3/or1ksim/tick/
333 small bug fixed markom 8265d 16h /or1k/tags/stable_0_2_0_rc3/or1ksim/tick/
332 removed fixed irq numbering from pic.h; tick timer section added markom 8265d 16h /or1k/tags/stable_0_2_0_rc3/or1ksim/tick/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.