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[/] [pairing/] [trunk/] - Rev 21

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Rev Log message Author Age Path
21 Add detailed input data capture condition in the document homer.xing 4512d 20h /pairing/trunk/
20 Add a module and a testbench for Xilinx ISE post-route simulation homer.xing 4513d 22h /pairing/trunk/
19 Update synthesis result homer.xing 4514d 16h /pairing/trunk/
18 add synthesis result homer.xing 4514d 16h /pairing/trunk/
17 use logic for $f3m_mux6$ homer.xing 4514d 17h /pairing/trunk/
16 Add synthesis configuration files homer.xing 4514d 21h /pairing/trunk/
15 add document. ha ha ha homer.xing 4514d 22h /pairing/trunk/
14 Move constraint file homer.xing 4514d 22h /pairing/trunk/
13 Add document and synthesis directories homer.xing 4514d 22h /pairing/trunk/
12 Simplify the interface of the core. homer.xing 4514d 23h /pairing/trunk/
11 Cheers! as fast as a rocket homer.xing 4515d 19h /pairing/trunk/
10 Ho ho, better circuit homer.xing 4516d 13h /pairing/trunk/
9 Add constrains file for ISE homer.xing 4517d 16h /pairing/trunk/
8 Finished Tate Pairing. Ha ha ha homer.xing 4517d 17h /pairing/trunk/
7 Finish inversion @ f33m homer.xing 4525d 22h /pairing/trunk/
6 add testbench for $f33m$. homer.xing 4526d 22h /pairing/trunk/
5 rename director : verilog/ -> rtl/ homer.xing 4526d 22h /pairing/trunk/
4 add testbench homer.xing 4527d 20h /pairing/trunk/
3 finish Duursma Lee algorithm. doing f33m module homer.xing 4527d 20h /pairing/trunk/
2 upload code for Duursma-Lee algorithm. I am still developing them. homer.xing 4528d 19h /pairing/trunk/
1 The project and the structure was created root 4528d 20h /pairing/trunk/

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