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[/] [pci/] [tags/] [asyst_2/] - Rev 116

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Rev Log message Author Age Path
116 Corrected bug when writing to FIFO (now it is registered). tadejm 7618d 07h /pci/tags/asyst_2/
115 Added signals for WB Master B3. tadejm 7618d 07h /pci/tags/asyst_2/
113 ifdefs moved to thier own lines, this confuses some of the tools. simons 7625d 10h /pci/tags/asyst_2/
111 synchronizer_flop replaced with pci_synchronizer_flop, artisan ram instance updated. simons 7625d 15h /pci/tags/asyst_2/
110 Module that converts slave WISHBONE B3 accesses to
WISHBONE B2 accesses with CAB.		 mihad 7627d 14h /pci/tags/asyst_2/
109 There was missing path to hdl.var file. tadejm 7631d 11h /pci/tags/asyst_2/
108 Added 'three_left_out' to pci_pciw_fifo signaling three locations before full. Added comparison between current registered cbe and next unregistered cbe to signal wb_master whether it is allowed to performe burst or not. Due to this, I needed 'three_left_out' so that writing to pci_pciw_fifo can be registered, otherwise timing problems would occure. tadejm 7631d 11h /pci/tags/asyst_2/
107 Added status when checking disconnect with or without data. Before it was only retry, now there is stop and retry. tadejm 7631d 12h /pci/tags/asyst_2/
106 Added limited WISHBONE B3 support for WISHBONE Slave Unit.
Doesn't support full speed bursts yet.		 mihad 7636d 10h /pci/tags/asyst_2/
105 Wrong pci_bridge32.v file included in the project! mihad 7641d 17h /pci/tags/asyst_2/
104 Found and simulated the problem in the synchronization logic.
Repaired the synchronization logic in the FIFOs.		 mihad 7641d 20h /pci/tags/asyst_2/
103 Added test application and modified files to support it. mihad 7688d 17h /pci/tags/asyst_2/
102 Cleanup! mihad 7688d 17h /pci/tags/asyst_2/
101 Added simulation files. mihad 7688d 17h /pci/tags/asyst_2/
100 Cleanup! mihad 7688d 17h /pci/tags/asyst_2/
99 Cleanup! mihad 7688d 18h /pci/tags/asyst_2/
98 Cleanup. mihad 7688d 18h /pci/tags/asyst_2/
97 Doing a little bit of cleanup. mihad 7688d 18h /pci/tags/asyst_2/
96 Update! mihad 7688d 18h /pci/tags/asyst_2/
95 Removed this file, because it was too large - long download time. mihad 7688d 18h /pci/tags/asyst_2/
94 Changed one critical PCI bus signal logic. mihad 7688d 18h /pci/tags/asyst_2/
93 Added a test application! mihad 7689d 01h /pci/tags/asyst_2/
92 Update! mihad 7689d 02h /pci/tags/asyst_2/
91 WebPack 5.2 constraint file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de) tadejm 7724d 15h /pci/tags/asyst_2/
90 WebPack 5.2 project file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de) tadejm 7724d 15h /pci/tags/asyst_2/
89 Burst 2 error fixed. mihad 7760d 16h /pci/tags/asyst_2/
88 Added the reset value parameter to the synchronizer flop module.
Added resets to all synchronizer flop instances.
Repaired initial sync value in fifos.		 mihad 7766d 15h /pci/tags/asyst_2/
87 Updated acording to RTL changes. mihad 7778d 13h /pci/tags/asyst_2/
86 Entered the option to disable no response counter in wb master. mihad 7778d 13h /pci/tags/asyst_2/
85 Changed Vendor ID defines. mihad 7778d 17h /pci/tags/asyst_2/

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