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[/] [pci/] [tags/] [asyst_2/] - Rev 132

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Rev Log message Author Age Path
132 Compact PCI Hot Swap support added.
New testcases added.
Specification updated.
Test application changed to support WB B3 cycles.		 mihad 7511d 08h /pci/tags/asyst_2/
131 Moved top.v to bench directory. Removed unneeded meta_flop,
modified files list files accordingly.		 mihad 7515d 07h /pci/tags/asyst_2/
130 The wbs B3 to B2 translation logic had wrong reset wire connected! mihad 7520d 08h /pci/tags/asyst_2/
128 Some warning cleanup. simons 7521d 10h /pci/tags/asyst_2/
126 ifdef - endif statements put in separate lines for flint compatibility. simons 7529d 03h /pci/tags/asyst_2/
124 Added missing signals to 2 sensitivity lists. Everything works the same as before. tadejm 7567d 10h /pci/tags/asyst_2/
122 mbist signals updated according to newest convention markom 7574d 10h /pci/tags/asyst_2/
119 Added support for WB B3. Some testcases were updated. tadejm 7630d 23h /pci/tags/asyst_2/
118 Some minor changes due to changes in core. tadejm 7630d 23h /pci/tags/asyst_2/
117 WB Master is now WISHBONE B3 compatible. tadejm 7630d 23h /pci/tags/asyst_2/
116 Corrected bug when writing to FIFO (now it is registered). tadejm 7630d 23h /pci/tags/asyst_2/
115 Added signals for WB Master B3. tadejm 7630d 23h /pci/tags/asyst_2/
113 ifdefs moved to thier own lines, this confuses some of the tools. simons 7638d 02h /pci/tags/asyst_2/
111 synchronizer_flop replaced with pci_synchronizer_flop, artisan ram instance updated. simons 7638d 07h /pci/tags/asyst_2/
110 Module that converts slave WISHBONE B3 accesses to
WISHBONE B2 accesses with CAB.		 mihad 7640d 06h /pci/tags/asyst_2/
109 There was missing path to hdl.var file. tadejm 7644d 03h /pci/tags/asyst_2/
108 Added 'three_left_out' to pci_pciw_fifo signaling three locations before full. Added comparison between current registered cbe and next unregistered cbe to signal wb_master whether it is allowed to performe burst or not. Due to this, I needed 'three_left_out' so that writing to pci_pciw_fifo can be registered, otherwise timing problems would occure. tadejm 7644d 03h /pci/tags/asyst_2/
107 Added status when checking disconnect with or without data. Before it was only retry, now there is stop and retry. tadejm 7644d 03h /pci/tags/asyst_2/
106 Added limited WISHBONE B3 support for WISHBONE Slave Unit.
Doesn't support full speed bursts yet.		 mihad 7649d 02h /pci/tags/asyst_2/
105 Wrong pci_bridge32.v file included in the project! mihad 7654d 09h /pci/tags/asyst_2/
104 Found and simulated the problem in the synchronization logic.
Repaired the synchronization logic in the FIFOs.		 mihad 7654d 11h /pci/tags/asyst_2/
103 Added test application and modified files to support it. mihad 7701d 09h /pci/tags/asyst_2/
102 Cleanup! mihad 7701d 09h /pci/tags/asyst_2/
101 Added simulation files. mihad 7701d 09h /pci/tags/asyst_2/
100 Cleanup! mihad 7701d 09h /pci/tags/asyst_2/
99 Cleanup! mihad 7701d 09h /pci/tags/asyst_2/
98 Cleanup. mihad 7701d 09h /pci/tags/asyst_2/
97 Doing a little bit of cleanup. mihad 7701d 09h /pci/tags/asyst_2/
96 Update! mihad 7701d 09h /pci/tags/asyst_2/
95 Removed this file, because it was too large - long download time. mihad 7701d 09h /pci/tags/asyst_2/

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