OpenCores
URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [asyst_2/] [rtl/] [verilog/] - Rev 94

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
94 Changed one critical PCI bus signal logic. mihad 7694d 21h /pci/tags/asyst_2/rtl/verilog/
88 Added the reset value parameter to the synchronizer flop module.
Added resets to all synchronizer flop instances.
Repaired initial sync value in fifos.		 mihad 7772d 18h /pci/tags/asyst_2/rtl/verilog/
86 Entered the option to disable no response counter in wb master. mihad 7784d 15h /pci/tags/asyst_2/rtl/verilog/
83 Cleaned up the code. No functional changes. mihad 7813d 13h /pci/tags/asyst_2/rtl/verilog/
81 Updated synchronization in top level fifo modules. mihad 7827d 09h /pci/tags/asyst_2/rtl/verilog/
79 Updated. mihad 7830d 14h /pci/tags/asyst_2/rtl/verilog/
78 Old files with wrong names removed. mihad 7830d 14h /pci/tags/asyst_2/rtl/verilog/
77 Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. mihad 7830d 14h /pci/tags/asyst_2/rtl/verilog/
73 Bug fixes, testcases added. mihad 7836d 15h /pci/tags/asyst_2/rtl/verilog/
72 *** empty log message *** mihad 7883d 19h /pci/tags/asyst_2/rtl/verilog/
71 Changed the code a bit to make it more readable.
Functionality not changed in any way.
More robust synchronization in fifos is still pending.		 mihad 7891d 10h /pci/tags/asyst_2/rtl/verilog/
69 Changed BIST signal names etc.. mihad 7928d 18h /pci/tags/asyst_2/rtl/verilog/
68 Changed wrong signal name scanb_sen into scanb_en. tadejm 7932d 03h /pci/tags/asyst_2/rtl/verilog/
67 Changed BIST signals for RAMs. tadejm 7932d 08h /pci/tags/asyst_2/rtl/verilog/
66 Changed empty status generation in pciw_fifo_control.v mihad 7935d 19h /pci/tags/asyst_2/rtl/verilog/
65 Cleaned up non-blocking assignments in combinatinal logic statements mihad 7938d 17h /pci/tags/asyst_2/rtl/verilog/
63 Added additional testcase and changed rst name in BIST to trst mihad 7938d 21h /pci/tags/asyst_2/rtl/verilog/
62 Added BIST signals for RAMs. mihad 7941d 14h /pci/tags/asyst_2/rtl/verilog/
60 Added support for Virtual Silicon two port RAM. Didn't run regression on it yet! mihad 7949d 14h /pci/tags/asyst_2/rtl/verilog/
59 Added meta flop module for easier meta stable FF identification during synthesis mihad 7949d 15h /pci/tags/asyst_2/rtl/verilog/
58 Removed all logic from asynchronous reset network mihad 7954d 15h /pci/tags/asyst_2/rtl/verilog/
57 Added completion expiration test for WB Slave unit. Changed expiration signalling mihad 7954d 21h /pci/tags/asyst_2/rtl/verilog/
56 Number of state bits define was removed mihad 7955d 12h /pci/tags/asyst_2/rtl/verilog/
55 Changed state machine encoding to true one-hot mihad 7955d 12h /pci/tags/asyst_2/rtl/verilog/
53 Updated for synthesis purposes. Gate level simulation was failing in some configurations mihad 7988d 18h /pci/tags/asyst_2/rtl/verilog/
51 Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions. mihad 7988d 22h /pci/tags/asyst_2/rtl/verilog/
50 Got rid of undef directives mihad 7991d 14h /pci/tags/asyst_2/rtl/verilog/
49 Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives mihad 7991d 14h /pci/tags/asyst_2/rtl/verilog/
48 Extracted distributed RAM module from wb/pci_tpram.v to its own file mihad 7991d 14h /pci/tags/asyst_2/rtl/verilog/
47 Known issues repaired mihad 7991d 20h /pci/tags/asyst_2/rtl/verilog/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.