OpenCores
URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [asyst_3/] - Rev 107

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
107 Added status when checking disconnect with or without data. Before it was only retry, now there is stop and retry. tadejm 7646d 11h /pci/tags/asyst_3/
106 Added limited WISHBONE B3 support for WISHBONE Slave Unit.
Doesn't support full speed bursts yet.		 mihad 7651d 10h /pci/tags/asyst_3/
105 Wrong pci_bridge32.v file included in the project! mihad 7656d 17h /pci/tags/asyst_3/
104 Found and simulated the problem in the synchronization logic.
Repaired the synchronization logic in the FIFOs.		 mihad 7656d 20h /pci/tags/asyst_3/
103 Added test application and modified files to support it. mihad 7703d 17h /pci/tags/asyst_3/
102 Cleanup! mihad 7703d 17h /pci/tags/asyst_3/
101 Added simulation files. mihad 7703d 17h /pci/tags/asyst_3/
100 Cleanup! mihad 7703d 17h /pci/tags/asyst_3/
99 Cleanup! mihad 7703d 17h /pci/tags/asyst_3/
98 Cleanup. mihad 7703d 17h /pci/tags/asyst_3/
97 Doing a little bit of cleanup. mihad 7703d 17h /pci/tags/asyst_3/
96 Update! mihad 7703d 18h /pci/tags/asyst_3/
95 Removed this file, because it was too large - long download time. mihad 7703d 18h /pci/tags/asyst_3/
94 Changed one critical PCI bus signal logic. mihad 7703d 18h /pci/tags/asyst_3/
93 Added a test application! mihad 7704d 01h /pci/tags/asyst_3/
92 Update! mihad 7704d 01h /pci/tags/asyst_3/
91 WebPack 5.2 constraint file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de) tadejm 7739d 15h /pci/tags/asyst_3/
90 WebPack 5.2 project file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de) tadejm 7739d 15h /pci/tags/asyst_3/
89 Burst 2 error fixed. mihad 7775d 16h /pci/tags/asyst_3/
88 Added the reset value parameter to the synchronizer flop module.
Added resets to all synchronizer flop instances.
Repaired initial sync value in fifos.		 mihad 7781d 15h /pci/tags/asyst_3/
87 Updated acording to RTL changes. mihad 7793d 12h /pci/tags/asyst_3/
86 Entered the option to disable no response counter in wb master. mihad 7793d 12h /pci/tags/asyst_3/
85 Changed Vendor ID defines. mihad 7793d 17h /pci/tags/asyst_3/
84 Changed vendor ID. mihad 7797d 11h /pci/tags/asyst_3/
83 Cleaned up the code. No functional changes. mihad 7822d 09h /pci/tags/asyst_3/
81 Updated synchronization in top level fifo modules. mihad 7836d 06h /pci/tags/asyst_3/
79 Updated. mihad 7839d 11h /pci/tags/asyst_3/
78 Old files with wrong names removed. mihad 7839d 11h /pci/tags/asyst_3/
77 Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. mihad 7839d 11h /pci/tags/asyst_3/
76 TRDY output delay was 10 instead of 11. Repaired. mihad 7842d 11h /pci/tags/asyst_3/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.