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[/] [pci/] [tags/] [asyst_3/] - Rev 88

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Rev Log message Author Age Path
88 Added the reset value parameter to the synchronizer flop module.
Added resets to all synchronizer flop instances.
Repaired initial sync value in fifos.		 mihad 7840d 19h /pci/tags/asyst_3/
87 Updated acording to RTL changes. mihad 7852d 17h /pci/tags/asyst_3/
86 Entered the option to disable no response counter in wb master. mihad 7852d 17h /pci/tags/asyst_3/
85 Changed Vendor ID defines. mihad 7852d 21h /pci/tags/asyst_3/
84 Changed vendor ID. mihad 7856d 15h /pci/tags/asyst_3/
83 Cleaned up the code. No functional changes. mihad 7881d 14h /pci/tags/asyst_3/
81 Updated synchronization in top level fifo modules. mihad 7895d 10h /pci/tags/asyst_3/
79 Updated. mihad 7898d 15h /pci/tags/asyst_3/
78 Old files with wrong names removed. mihad 7898d 15h /pci/tags/asyst_3/
77 Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. mihad 7898d 15h /pci/tags/asyst_3/
76 TRDY output delay was 10 instead of 11. Repaired. mihad 7901d 15h /pci/tags/asyst_3/
75 Include statement moved out of off/on pragma as reported by Uwe. mihad 7904d 16h /pci/tags/asyst_3/
73 Bug fixes, testcases added. mihad 7904d 16h /pci/tags/asyst_3/
72 *** empty log message *** mihad 7951d 20h /pci/tags/asyst_3/
71 Changed the code a bit to make it more readable.
Functionality not changed in any way.
More robust synchronization in fifos is still pending.		 mihad 7959d 12h /pci/tags/asyst_3/
69 Changed BIST signal names etc.. mihad 7996d 19h /pci/tags/asyst_3/
68 Changed wrong signal name scanb_sen into scanb_en. tadejm 8000d 05h /pci/tags/asyst_3/
67 Changed BIST signals for RAMs. tadejm 8000d 09h /pci/tags/asyst_3/
66 Changed empty status generation in pciw_fifo_control.v mihad 8003d 20h /pci/tags/asyst_3/
65 Cleaned up non-blocking assignments in combinatinal logic statements mihad 8006d 18h /pci/tags/asyst_3/
64 The testcase I just added in previous revision repaired mihad 8006d 20h /pci/tags/asyst_3/
63 Added additional testcase and changed rst name in BIST to trst mihad 8006d 22h /pci/tags/asyst_3/
62 Added BIST signals for RAMs. mihad 8009d 15h /pci/tags/asyst_3/
60 Added support for Virtual Silicon two port RAM. Didn't run regression on it yet! mihad 8017d 15h /pci/tags/asyst_3/
59 Added meta flop module for easier meta stable FF identification during synthesis mihad 8017d 16h /pci/tags/asyst_3/
58 Removed all logic from asynchronous reset network mihad 8022d 16h /pci/tags/asyst_3/
57 Added completion expiration test for WB Slave unit. Changed expiration signalling mihad 8022d 22h /pci/tags/asyst_3/
56 Number of state bits define was removed mihad 8023d 13h /pci/tags/asyst_3/
55 Changed state machine encoding to true one-hot mihad 8023d 14h /pci/tags/asyst_3/
54 Changed Tsetup and Thold for WISHBONE models, due to difficulties encountered during gate level sim mihad 8056d 15h /pci/tags/asyst_3/

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