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[/] [pci/] [tags/] [asyst_3/] [rtl/] - Rev 154

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Rev Log message Author Age Path
154 New directory structure. root 5620d 10h /pci/tags/asyst_3/rtl/
134 This commit was manufactured by cvs2svn to create tag 'asyst_3'. 7528d 07h /pci/tags/asyst_3/rtl/
132 Compact PCI Hot Swap support added.
New testcases added.
Specification updated.
Test application changed to support WB B3 cycles.		 mihad 7528d 07h /pci/tags/asyst_3/rtl/
131 Moved top.v to bench directory. Removed unneeded meta_flop,
modified files list files accordingly.		 mihad 7532d 06h /pci/tags/asyst_3/rtl/
130 The wbs B3 to B2 translation logic had wrong reset wire connected! mihad 7537d 06h /pci/tags/asyst_3/rtl/
128 Some warning cleanup. simons 7538d 09h /pci/tags/asyst_3/rtl/
126 ifdef - endif statements put in separate lines for flint compatibility. simons 7546d 02h /pci/tags/asyst_3/rtl/
124 Added missing signals to 2 sensitivity lists. Everything works the same as before. tadejm 7584d 09h /pci/tags/asyst_3/rtl/
122 mbist signals updated according to newest convention markom 7591d 09h /pci/tags/asyst_3/rtl/
117 WB Master is now WISHBONE B3 compatible. tadejm 7647d 21h /pci/tags/asyst_3/rtl/
116 Corrected bug when writing to FIFO (now it is registered). tadejm 7647d 21h /pci/tags/asyst_3/rtl/
115 Added signals for WB Master B3. tadejm 7647d 21h /pci/tags/asyst_3/rtl/
113 ifdefs moved to thier own lines, this confuses some of the tools. simons 7655d 00h /pci/tags/asyst_3/rtl/
111 synchronizer_flop replaced with pci_synchronizer_flop, artisan ram instance updated. simons 7655d 05h /pci/tags/asyst_3/rtl/
110 Module that converts slave WISHBONE B3 accesses to
WISHBONE B2 accesses with CAB.		 mihad 7657d 04h /pci/tags/asyst_3/rtl/
108 Added 'three_left_out' to pci_pciw_fifo signaling three locations before full. Added comparison between current registered cbe and next unregistered cbe to signal wb_master whether it is allowed to performe burst or not. Due to this, I needed 'three_left_out' so that writing to pci_pciw_fifo can be registered, otherwise timing problems would occure. tadejm 7661d 02h /pci/tags/asyst_3/rtl/
106 Added limited WISHBONE B3 support for WISHBONE Slave Unit.
Doesn't support full speed bursts yet.		 mihad 7666d 00h /pci/tags/asyst_3/rtl/
104 Found and simulated the problem in the synchronization logic.
Repaired the synchronization logic in the FIFOs.		 mihad 7671d 10h /pci/tags/asyst_3/rtl/
94 Changed one critical PCI bus signal logic. mihad 7718d 08h /pci/tags/asyst_3/rtl/
88 Added the reset value parameter to the synchronizer flop module.
Added resets to all synchronizer flop instances.
Repaired initial sync value in fifos.		 mihad 7796d 05h /pci/tags/asyst_3/rtl/
86 Entered the option to disable no response counter in wb master. mihad 7808d 03h /pci/tags/asyst_3/rtl/
83 Cleaned up the code. No functional changes. mihad 7837d 00h /pci/tags/asyst_3/rtl/
81 Updated synchronization in top level fifo modules. mihad 7850d 20h /pci/tags/asyst_3/rtl/
79 Updated. mihad 7854d 01h /pci/tags/asyst_3/rtl/
78 Old files with wrong names removed. mihad 7854d 01h /pci/tags/asyst_3/rtl/
77 Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. mihad 7854d 01h /pci/tags/asyst_3/rtl/
73 Bug fixes, testcases added. mihad 7860d 02h /pci/tags/asyst_3/rtl/
72 *** empty log message *** mihad 7907d 06h /pci/tags/asyst_3/rtl/
71 Changed the code a bit to make it more readable.
Functionality not changed in any way.
More robust synchronization in fifos is still pending.		 mihad 7914d 22h /pci/tags/asyst_3/rtl/
69 Changed BIST signal names etc.. mihad 7952d 05h /pci/tags/asyst_3/rtl/

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