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[/] [pci/] [tags/] [rel_00/] - Rev 33

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Rev Log message Author Age Path
33 Added some testcases, removed un-needed fifo signals mihad 8169d 03h /pci/tags/rel_00/
32 Added include statement that was missing and causing errors mihad 8177d 00h /pci/tags/rel_00/
31 User defined constants used for Test Application tadej 8179d 19h /pci/tags/rel_00/
30 Example of PCI testbench log file mihad 8180d 03h /pci/tags/rel_00/
29 Xilinx synthesys log file tadej 8180d 06h /pci/tags/rel_00/
28 pci/doc/pci_databook.pdf tadej 8181d 01h /pci/tags/rel_00/
27 Modified testbench and fixed some bugs mihad 8182d 22h /pci/tags/rel_00/
26 Modified testbench and fixed some bugs mihad 8182d 23h /pci/tags/rel_00/
25 *** empty log message *** mihad 8200d 21h /pci/tags/rel_00/
24 *** empty log message *** mihad 8200d 21h /pci/tags/rel_00/
23 *** empty log message *** mihad 8200d 23h /pci/tags/rel_00/
22 Added short description for simulation running mihad 8200d 23h /pci/tags/rel_00/
21 Repaired a few bugs, updated specification, added test bench files and design document mihad 8201d 00h /pci/tags/rel_00/
20 *** empty log message *** mihad 8201d 00h /pci/tags/rel_00/
19 *** empty log message *** mihad 8201d 00h /pci/tags/rel_00/
18 *** empty log message *** mihad 8201d 00h /pci/tags/rel_00/
17 *** empty log message *** mihad 8201d 01h /pci/tags/rel_00/
16 Import of various scripts for simulation running mihad 8201d 01h /pci/tags/rel_00/
15 Initial testbench import. Still under development mihad 8201d 01h /pci/tags/rel_00/
14 *** empty log message *** mihad 8201d 02h /pci/tags/rel_00/
13 Added separate software directory to the project mihad 8201d 02h /pci/tags/rel_00/
12 PCI IP Core Introduction mihad 8202d 21h /pci/tags/rel_00/
11 Initial design document release mihad 8202d 21h /pci/tags/rel_00/
10 Updated descriptions, functional changes, added software obligations chapter mihad 8202d 22h /pci/tags/rel_00/
9 Update the Configuration Space and REGISTERS description mihad 8303d 06h /pci/tags/rel_00/
7 Updated all files with inclusion of timescale file for simulation purposes. mihad 8320d 07h /pci/tags/rel_00/
6 Updated all files with inclusion of timescale file for simulation purposes. mihad 8320d 07h /pci/tags/rel_00/
5 Added .o file for kernel 2.4.3 mihad 8322d 22h /pci/tags/rel_00/
3 New project directory structure mihad 8322d 23h /pci/tags/rel_00/
2 New project directory structure mihad 8323d 00h /pci/tags/rel_00/

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