URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_1/] - Rev 54

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Rev	Log message	Author	Age	Path
54	Changed Tsetup and Thold for WISHBONE models, due to difficulties encountered during gate level sim	mihad	7980d 23h	/pci/tags/rel_1/
53	Updated for synthesis purposes. Gate level simulation was failing in some configurations	mihad	7981d 02h	/pci/tags/rel_1/
52	Oops, never before noticed that OC header is missing	mihad	7981d 06h	/pci/tags/rel_1/
51	Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions.	mihad	7981d 07h	/pci/tags/rel_1/
50	Got rid of undef directives	mihad	7983d 23h	/pci/tags/rel_1/
49	Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives	mihad	7983d 23h	/pci/tags/rel_1/
48	Extracted distributed RAM module from wb/pci_tpram.v to its own file	mihad	7983d 23h	/pci/tags/rel_1/
47	Known issues repaired	mihad	7984d 05h	/pci/tags/rel_1/
46	Include statement was enclosed in synosys translate off/on directive - repaired	mihad	7988d 23h	/pci/tags/rel_1/
45	Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image	mihad	7990d 05h	/pci/tags/rel_1/
44	Added for testing of Configuration Cycles Type 1	mihad	7990d 05h	/pci/tags/rel_1/
43	Removed - Interrupt acknowledge cycle now accepted by pci_behaviorial_device	mihad	7990d 05h	/pci/tags/rel_1/
42	Removed out of date files	mihad	8002d 06h	/pci/tags/rel_1/
40	From these Wrod files PDF were created - added future improvements	tadej	8080d 20h	/pci/tags/rel_1/
39	File not needed	tadej	8080d 21h	/pci/tags/rel_1/
38	This file is not needed	tadej	8081d 00h	/pci/tags/rel_1/
37	These files are not needed any more	tadej	8081d 00h	/pci/tags/rel_1/
36	* empty log message *	tadej	8081d 01h	/pci/tags/rel_1/
35	Files updated with missing includes, resolved some race conditions in test bench	mihad	8135d 08h	/pci/tags/rel_1/
34	Added missing include statements	mihad	8150d 07h	/pci/tags/rel_1/
33	Added some testcases, removed un-needed fifo signals	mihad	8151d 04h	/pci/tags/rel_1/
32	Added include statement that was missing and causing errors	mihad	8159d 00h	/pci/tags/rel_1/
31	User defined constants used for Test Application	tadej	8161d 19h	/pci/tags/rel_1/
30	Example of PCI testbench log file	mihad	8162d 04h	/pci/tags/rel_1/
29	Xilinx synthesys log file	tadej	8162d 06h	/pci/tags/rel_1/
28	pci/doc/pci_databook.pdf	tadej	8163d 01h	/pci/tags/rel_1/
27	Modified testbench and fixed some bugs	mihad	8164d 23h	/pci/tags/rel_1/
26	Modified testbench and fixed some bugs	mihad	8164d 23h	/pci/tags/rel_1/
25	* empty log message *	mihad	8182d 22h	/pci/tags/rel_1/
24	* empty log message *	mihad	8182d 22h	/pci/tags/rel_1/

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[/] [pci/] [tags/] [rel_1/] - Rev 54

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