OpenCores
URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_10/] - Rev 100

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
100 Cleanup! mihad 7684d 23h /pci/tags/rel_10/
99 Cleanup! mihad 7684d 23h /pci/tags/rel_10/
98 Cleanup. mihad 7684d 23h /pci/tags/rel_10/
97 Doing a little bit of cleanup. mihad 7684d 23h /pci/tags/rel_10/
96 Update! mihad 7684d 23h /pci/tags/rel_10/
95 Removed this file, because it was too large - long download time. mihad 7684d 23h /pci/tags/rel_10/
94 Changed one critical PCI bus signal logic. mihad 7684d 23h /pci/tags/rel_10/
93 Added a test application! mihad 7685d 07h /pci/tags/rel_10/
92 Update! mihad 7685d 07h /pci/tags/rel_10/
91 WebPack 5.2 constraint file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de) tadejm 7720d 21h /pci/tags/rel_10/
90 WebPack 5.2 project file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de) tadejm 7720d 21h /pci/tags/rel_10/
89 Burst 2 error fixed. mihad 7756d 21h /pci/tags/rel_10/
88 Added the reset value parameter to the synchronizer flop module.
Added resets to all synchronizer flop instances.
Repaired initial sync value in fifos.		 mihad 7762d 20h /pci/tags/rel_10/
87 Updated acording to RTL changes. mihad 7774d 18h /pci/tags/rel_10/
86 Entered the option to disable no response counter in wb master. mihad 7774d 18h /pci/tags/rel_10/
85 Changed Vendor ID defines. mihad 7774d 22h /pci/tags/rel_10/
84 Changed vendor ID. mihad 7778d 17h /pci/tags/rel_10/
83 Cleaned up the code. No functional changes. mihad 7803d 15h /pci/tags/rel_10/
81 Updated synchronization in top level fifo modules. mihad 7817d 12h /pci/tags/rel_10/
79 Updated. mihad 7820d 17h /pci/tags/rel_10/
78 Old files with wrong names removed. mihad 7820d 17h /pci/tags/rel_10/
77 Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. mihad 7820d 17h /pci/tags/rel_10/
76 TRDY output delay was 10 instead of 11. Repaired. mihad 7823d 16h /pci/tags/rel_10/
75 Include statement moved out of off/on pragma as reported by Uwe. mihad 7826d 17h /pci/tags/rel_10/
73 Bug fixes, testcases added. mihad 7826d 18h /pci/tags/rel_10/
72 *** empty log message *** mihad 7873d 21h /pci/tags/rel_10/
71 Changed the code a bit to make it more readable.
Functionality not changed in any way.
More robust synchronization in fifos is still pending.		 mihad 7881d 13h /pci/tags/rel_10/
69 Changed BIST signal names etc.. mihad 7918d 21h /pci/tags/rel_10/
68 Changed wrong signal name scanb_sen into scanb_en. tadejm 7922d 06h /pci/tags/rel_10/
67 Changed BIST signals for RAMs. tadejm 7922d 11h /pci/tags/rel_10/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.