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[/] [pci/] [tags/] [rel_10/] - Rev 107

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Rev Log message Author Age Path
107 Added status when checking disconnect with or without data. Before it was only retry, now there is stop and retry. tadejm 7668d 12h /pci/tags/rel_10/
106 Added limited WISHBONE B3 support for WISHBONE Slave Unit.
Doesn't support full speed bursts yet.		 mihad 7673d 10h /pci/tags/rel_10/
105 Wrong pci_bridge32.v file included in the project! mihad 7678d 18h /pci/tags/rel_10/
104 Found and simulated the problem in the synchronization logic.
Repaired the synchronization logic in the FIFOs.		 mihad 7678d 20h /pci/tags/rel_10/
103 Added test application and modified files to support it. mihad 7725d 17h /pci/tags/rel_10/
102 Cleanup! mihad 7725d 17h /pci/tags/rel_10/
101 Added simulation files. mihad 7725d 17h /pci/tags/rel_10/
100 Cleanup! mihad 7725d 18h /pci/tags/rel_10/
99 Cleanup! mihad 7725d 18h /pci/tags/rel_10/
98 Cleanup. mihad 7725d 18h /pci/tags/rel_10/
97 Doing a little bit of cleanup. mihad 7725d 18h /pci/tags/rel_10/
96 Update! mihad 7725d 18h /pci/tags/rel_10/
95 Removed this file, because it was too large - long download time. mihad 7725d 18h /pci/tags/rel_10/
94 Changed one critical PCI bus signal logic. mihad 7725d 18h /pci/tags/rel_10/
93 Added a test application! mihad 7726d 01h /pci/tags/rel_10/
92 Update! mihad 7726d 02h /pci/tags/rel_10/
91 WebPack 5.2 constraint file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de) tadejm 7761d 16h /pci/tags/rel_10/
90 WebPack 5.2 project file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de) tadejm 7761d 16h /pci/tags/rel_10/
89 Burst 2 error fixed. mihad 7797d 16h /pci/tags/rel_10/
88 Added the reset value parameter to the synchronizer flop module.
Added resets to all synchronizer flop instances.
Repaired initial sync value in fifos.		 mihad 7803d 15h /pci/tags/rel_10/
87 Updated acording to RTL changes. mihad 7815d 13h /pci/tags/rel_10/
86 Entered the option to disable no response counter in wb master. mihad 7815d 13h /pci/tags/rel_10/
85 Changed Vendor ID defines. mihad 7815d 17h /pci/tags/rel_10/
84 Changed vendor ID. mihad 7819d 11h /pci/tags/rel_10/
83 Cleaned up the code. No functional changes. mihad 7844d 10h /pci/tags/rel_10/
81 Updated synchronization in top level fifo modules. mihad 7858d 06h /pci/tags/rel_10/
79 Updated. mihad 7861d 11h /pci/tags/rel_10/
78 Old files with wrong names removed. mihad 7861d 12h /pci/tags/rel_10/
77 Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. mihad 7861d 12h /pci/tags/rel_10/
76 TRDY output delay was 10 instead of 11. Repaired. mihad 7864d 11h /pci/tags/rel_10/

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