OpenCores
URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_10/] - Rev 57

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
57 Added completion expiration test for WB Slave unit. Changed expiration signalling mihad 7966d 07h /pci/tags/rel_10/
56 Number of state bits define was removed mihad 7966d 22h /pci/tags/rel_10/
55 Changed state machine encoding to true one-hot mihad 7966d 23h /pci/tags/rel_10/
54 Changed Tsetup and Thold for WISHBONE models, due to difficulties encountered during gate level sim mihad 8000d 00h /pci/tags/rel_10/
53 Updated for synthesis purposes. Gate level simulation was failing in some configurations mihad 8000d 04h /pci/tags/rel_10/
52 Oops, never before noticed that OC header is missing mihad 8000d 08h /pci/tags/rel_10/
51 Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions. mihad 8000d 08h /pci/tags/rel_10/
50 Got rid of undef directives mihad 8003d 00h /pci/tags/rel_10/
49 Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives mihad 8003d 00h /pci/tags/rel_10/
48 Extracted distributed RAM module from wb/pci_tpram.v to its own file mihad 8003d 01h /pci/tags/rel_10/
47 Known issues repaired mihad 8003d 06h /pci/tags/rel_10/
46 Include statement was enclosed in synosys translate off/on directive - repaired mihad 8008d 01h /pci/tags/rel_10/
45 Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image mihad 8009d 06h /pci/tags/rel_10/
44 Added for testing of Configuration Cycles Type 1 mihad 8009d 07h /pci/tags/rel_10/
43 Removed - Interrupt acknowledge cycle now accepted by pci_behaviorial_device mihad 8009d 07h /pci/tags/rel_10/
42 Removed out of date files mihad 8021d 07h /pci/tags/rel_10/
40 From these Wrod files PDF were created - added future improvements tadej 8099d 22h /pci/tags/rel_10/
39 File not needed tadej 8099d 23h /pci/tags/rel_10/
38 This file is not needed tadej 8100d 02h /pci/tags/rel_10/
37 These files are not needed any more tadej 8100d 02h /pci/tags/rel_10/
36 *** empty log message *** tadej 8100d 02h /pci/tags/rel_10/
35 Files updated with missing includes, resolved some race conditions in test bench mihad 8154d 10h /pci/tags/rel_10/
34 Added missing include statements mihad 8169d 08h /pci/tags/rel_10/
33 Added some testcases, removed un-needed fifo signals mihad 8170d 05h /pci/tags/rel_10/
32 Added include statement that was missing and causing errors mihad 8178d 02h /pci/tags/rel_10/
31 User defined constants used for Test Application tadej 8180d 21h /pci/tags/rel_10/
30 Example of PCI testbench log file mihad 8181d 05h /pci/tags/rel_10/
29 Xilinx synthesys log file tadej 8181d 08h /pci/tags/rel_10/
28 pci/doc/pci_databook.pdf tadej 8182d 03h /pci/tags/rel_10/
27 Modified testbench and fixed some bugs mihad 8184d 00h /pci/tags/rel_10/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.