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[/] [pci/] [tags/] [rel_10/] - Rev 72

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Rev Log message Author Age Path
72 *** empty log message *** mihad 7876d 08h /pci/tags/rel_10/
71 Changed the code a bit to make it more readable.
Functionality not changed in any way.
More robust synchronization in fifos is still pending.		 mihad 7883d 23h /pci/tags/rel_10/
69 Changed BIST signal names etc.. mihad 7921d 07h /pci/tags/rel_10/
68 Changed wrong signal name scanb_sen into scanb_en. tadejm 7924d 16h /pci/tags/rel_10/
67 Changed BIST signals for RAMs. tadejm 7924d 21h /pci/tags/rel_10/
66 Changed empty status generation in pciw_fifo_control.v mihad 7928d 08h /pci/tags/rel_10/
65 Cleaned up non-blocking assignments in combinatinal logic statements mihad 7931d 06h /pci/tags/rel_10/
64 The testcase I just added in previous revision repaired mihad 7931d 08h /pci/tags/rel_10/
63 Added additional testcase and changed rst name in BIST to trst mihad 7931d 10h /pci/tags/rel_10/
62 Added BIST signals for RAMs. mihad 7934d 03h /pci/tags/rel_10/
60 Added support for Virtual Silicon two port RAM. Didn't run regression on it yet! mihad 7942d 03h /pci/tags/rel_10/
59 Added meta flop module for easier meta stable FF identification during synthesis mihad 7942d 04h /pci/tags/rel_10/
58 Removed all logic from asynchronous reset network mihad 7947d 04h /pci/tags/rel_10/
57 Added completion expiration test for WB Slave unit. Changed expiration signalling mihad 7947d 10h /pci/tags/rel_10/
56 Number of state bits define was removed mihad 7948d 01h /pci/tags/rel_10/
55 Changed state machine encoding to true one-hot mihad 7948d 02h /pci/tags/rel_10/
54 Changed Tsetup and Thold for WISHBONE models, due to difficulties encountered during gate level sim mihad 7981d 03h /pci/tags/rel_10/
53 Updated for synthesis purposes. Gate level simulation was failing in some configurations mihad 7981d 07h /pci/tags/rel_10/
52 Oops, never before noticed that OC header is missing mihad 7981d 11h /pci/tags/rel_10/
51 Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions. mihad 7981d 11h /pci/tags/rel_10/
50 Got rid of undef directives mihad 7984d 03h /pci/tags/rel_10/
49 Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives mihad 7984d 03h /pci/tags/rel_10/
48 Extracted distributed RAM module from wb/pci_tpram.v to its own file mihad 7984d 03h /pci/tags/rel_10/
47 Known issues repaired mihad 7984d 09h /pci/tags/rel_10/
46 Include statement was enclosed in synosys translate off/on directive - repaired mihad 7989d 03h /pci/tags/rel_10/
45 Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image mihad 7990d 09h /pci/tags/rel_10/
44 Added for testing of Configuration Cycles Type 1 mihad 7990d 10h /pci/tags/rel_10/
43 Removed - Interrupt acknowledge cycle now accepted by pci_behaviorial_device mihad 7990d 10h /pci/tags/rel_10/
42 Removed out of date files mihad 8002d 10h /pci/tags/rel_10/
40 From these Wrod files PDF were created - added future improvements tadej 8081d 01h /pci/tags/rel_10/

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