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[/] [pci/] [tags/] [rel_10/] - Rev 77

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Rev Log message Author Age Path
77 Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. mihad 7863d 02h /pci/tags/rel_10/
76 TRDY output delay was 10 instead of 11. Repaired. mihad 7866d 02h /pci/tags/rel_10/
75 Include statement moved out of off/on pragma as reported by Uwe. mihad 7869d 03h /pci/tags/rel_10/
73 Bug fixes, testcases added. mihad 7869d 03h /pci/tags/rel_10/
72 *** empty log message *** mihad 7916d 07h /pci/tags/rel_10/
71 Changed the code a bit to make it more readable.
Functionality not changed in any way.
More robust synchronization in fifos is still pending.		 mihad 7923d 22h /pci/tags/rel_10/
69 Changed BIST signal names etc.. mihad 7961d 06h /pci/tags/rel_10/
68 Changed wrong signal name scanb_sen into scanb_en. tadejm 7964d 15h /pci/tags/rel_10/
67 Changed BIST signals for RAMs. tadejm 7964d 20h /pci/tags/rel_10/
66 Changed empty status generation in pciw_fifo_control.v mihad 7968d 07h /pci/tags/rel_10/
65 Cleaned up non-blocking assignments in combinatinal logic statements mihad 7971d 05h /pci/tags/rel_10/
64 The testcase I just added in previous revision repaired mihad 7971d 07h /pci/tags/rel_10/
63 Added additional testcase and changed rst name in BIST to trst mihad 7971d 09h /pci/tags/rel_10/
62 Added BIST signals for RAMs. mihad 7974d 02h /pci/tags/rel_10/
60 Added support for Virtual Silicon two port RAM. Didn't run regression on it yet! mihad 7982d 02h /pci/tags/rel_10/
59 Added meta flop module for easier meta stable FF identification during synthesis mihad 7982d 03h /pci/tags/rel_10/
58 Removed all logic from asynchronous reset network mihad 7987d 03h /pci/tags/rel_10/
57 Added completion expiration test for WB Slave unit. Changed expiration signalling mihad 7987d 09h /pci/tags/rel_10/
56 Number of state bits define was removed mihad 7988d 00h /pci/tags/rel_10/
55 Changed state machine encoding to true one-hot mihad 7988d 00h /pci/tags/rel_10/
54 Changed Tsetup and Thold for WISHBONE models, due to difficulties encountered during gate level sim mihad 8021d 02h /pci/tags/rel_10/
53 Updated for synthesis purposes. Gate level simulation was failing in some configurations mihad 8021d 05h /pci/tags/rel_10/
52 Oops, never before noticed that OC header is missing mihad 8021d 10h /pci/tags/rel_10/
51 Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions. mihad 8021d 10h /pci/tags/rel_10/
50 Got rid of undef directives mihad 8024d 02h /pci/tags/rel_10/
49 Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives mihad 8024d 02h /pci/tags/rel_10/
48 Extracted distributed RAM module from wb/pci_tpram.v to its own file mihad 8024d 02h /pci/tags/rel_10/
47 Known issues repaired mihad 8024d 08h /pci/tags/rel_10/
46 Include statement was enclosed in synosys translate off/on directive - repaired mihad 8029d 02h /pci/tags/rel_10/
45 Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image mihad 8030d 08h /pci/tags/rel_10/

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