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[/] [pci/] [tags/] [rel_10/] - Rev 88

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Rev	Log message	Author	Age	Path
88	Added the reset value parameter to the synchronizer flop module. Added resets to all synchronizer flop instances. Repaired initial sync value in fifos.	mihad	7765d 09h	/pci/tags/rel_10/
87	Updated acording to RTL changes.	mihad	7777d 07h	/pci/tags/rel_10/
86	Entered the option to disable no response counter in wb master.	mihad	7777d 07h	/pci/tags/rel_10/
85	Changed Vendor ID defines.	mihad	7777d 11h	/pci/tags/rel_10/
84	Changed vendor ID.	mihad	7781d 06h	/pci/tags/rel_10/
83	Cleaned up the code. No functional changes.	mihad	7806d 04h	/pci/tags/rel_10/
81	Updated synchronization in top level fifo modules.	mihad	7820d 00h	/pci/tags/rel_10/
79	Updated.	mihad	7823d 05h	/pci/tags/rel_10/
78	Old files with wrong names removed.	mihad	7823d 06h	/pci/tags/rel_10/
77	Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.	mihad	7823d 06h	/pci/tags/rel_10/
76	TRDY output delay was 10 instead of 11. Repaired.	mihad	7826d 05h	/pci/tags/rel_10/
75	Include statement moved out of off/on pragma as reported by Uwe.	mihad	7829d 06h	/pci/tags/rel_10/
73	Bug fixes, testcases added.	mihad	7829d 06h	/pci/tags/rel_10/
72	* empty log message *	mihad	7876d 10h	/pci/tags/rel_10/
71	Changed the code a bit to make it more readable. Functionality not changed in any way. More robust synchronization in fifos is still pending.	mihad	7884d 02h	/pci/tags/rel_10/
69	Changed BIST signal names etc..	mihad	7921d 09h	/pci/tags/rel_10/
68	Changed wrong signal name scanb_sen into scanb_en.	tadejm	7924d 19h	/pci/tags/rel_10/
67	Changed BIST signals for RAMs.	tadejm	7925d 00h	/pci/tags/rel_10/
66	Changed empty status generation in pciw_fifo_control.v	mihad	7928d 10h	/pci/tags/rel_10/
65	Cleaned up non-blocking assignments in combinatinal logic statements	mihad	7931d 08h	/pci/tags/rel_10/
64	The testcase I just added in previous revision repaired	mihad	7931d 10h	/pci/tags/rel_10/
63	Added additional testcase and changed rst name in BIST to trst	mihad	7931d 12h	/pci/tags/rel_10/
62	Added BIST signals for RAMs.	mihad	7934d 05h	/pci/tags/rel_10/
60	Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!	mihad	7942d 05h	/pci/tags/rel_10/
59	Added meta flop module for easier meta stable FF identification during synthesis	mihad	7942d 06h	/pci/tags/rel_10/
58	Removed all logic from asynchronous reset network	mihad	7947d 07h	/pci/tags/rel_10/
57	Added completion expiration test for WB Slave unit. Changed expiration signalling	mihad	7947d 13h	/pci/tags/rel_10/
56	Number of state bits define was removed	mihad	7948d 03h	/pci/tags/rel_10/
55	Changed state machine encoding to true one-hot	mihad	7948d 04h	/pci/tags/rel_10/
54	Changed Tsetup and Thold for WISHBONE models, due to difficulties encountered during gate level sim	mihad	7981d 06h	/pci/tags/rel_10/

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[/] [pci/] [tags/] [rel_10/] - Rev 88

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